A latch circuit includes a plurality of latch sets, each including an enable latch and a plurality of address latches; and a plurality of latch-width adjusting circuits respectively corresponding to the latch sets, wherein, in each of the plurality of latch sets, the corresponding latch-width adjusting circuit is disposed between the enable latch of the corresponding latch set and the address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch depending on whether or not the corresponding latch set is used, at an end of a boot-up operation.

A latch circuit includes a plurality of latch sets, each including an enable latch and a plurality of address latches; and a plurality of latch-width adjusting circuits respectively corresponding to the latch sets, wherein, in each of the plurality of latch sets, the corresponding latch-width adjusting circuit is disposed between the enable latch of the corresponding latch set and the address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch depending on whether or not the corresponding latch set is used, at an end of a boot-up operation.

Various embodiments include a memory device that is capable of performing memory access operations with reduced power consumption relative to prior approaches. The memory device receives early indication as to whether a forthcoming memory access operation is a read operation or a write operation. The memory device enables various circuits and disables other circuits depending on whether this early indication identifies an upcoming memory access operation as a read operation or a write operation. As a result, circuits that are not needed for an upcoming memory access operation are disabled earlier during the memory access operation relative to prior approaches. Disabling such circuits earlier during the memory access operation reduces power consumption without reducing memory device performance.

Disclosed is a method for accessing memory cells arranged in rows and columns. The method includes activating a specific row of the rows of the memory cells, and flipping data bits stored in memory cells of the specific row in response to determining that concentrated activation occurs at the specific row.

Disclosed is a method for accessing memory cells arranged in rows and columns. The method includes activating a specific row of the rows of the memory cells, and flipping data bits stored in memory cells of the specific row in response to determining that concentrated activation occurs at the specific row.

A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.

An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

A memory device includes a plurality of memory cells each including a semiconductor base material that stands on a substrate in a vertical direction or that extends in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a memory write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a memory erase operation of discharging the group of positive holes from inside the channel semiconductor layer, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line, a voltage of the word line changes from a first voltage to a second voltage that is higher than the first voltage, and a voltage of the bit lines subsequently change from a third voltage to a fourth voltage that is higher than the third voltage to perform a memory read operation of reading to the bit lines, pieces of storage data in a plurality of semiconductor base materials selected by the word line.

A semiconductor memory training method includes: selecting two adjacent reference voltages from a plurality of reference voltages as a first reference voltage and a second reference voltage; obtaining a first minimum margin value for the plurality of target signal lines under the first reference voltage; obtaining a second minimum margin value for the plurality of target signal lines under the second reference voltage, according to a minimum margin value for each target signal line under the second reference voltage; determining a target interval for an expected margin value according to the first minimum margin value and the second minimum margin value, the expected margin value being the maximum one among the minimum margin values for the plurality of target signal lines under the plurality of reference voltages; and searching for the expected margin value in the target interval.