An input sampling method includes the following operations. A first pulse signal and a second pulse signal are received. Logical operation is performed on the first pulse signal and the second pulse signal to determine a to-be-sampled signal. The to-be-sampled signal is obtained by shielding an invalid part of the second pulse signal according to a logical operation result. Sampling process is performed on the to-be-sampled signal to obtain a target sampled signal.

A semiconductor memory device is provided. The semiconductor memory device can suppress increases in power consumption. As a result, damage to the data normally caused by row problems can be prevented. The semiconductor memory device includes a control unit. The control unit controls the time interval for refreshing the memory. If the frequency of a read/write access requirement to the memory during a predetermined period is higher, then the control unit shortens the interval between memory refresh operations.

A semiconductor memory apparatus includes a first memory cell array, a second memory cell array, and a hammering control circuit. The first memory cell array includes a first row hammer memory cell. The second memory cell array includes a second row hammer memory cell. The hammering control circuit controls the number of active operations on a first word line to be stored in the second row hammer memory cell and controls the number of active operations on a second word line to be stored in the first row hammer memory cell.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom.

Systems and methods for detecting a row hammer in a memory comprising a plurality of memory cells arranged in a plurality of rows may include: a plurality of detection cells in a subject row of memory cells, the detection cells to be set to respective initial states and configured to transition to a state different from their initial states in response to activations of memory cells in an adjacent row of memory cells; a comparison circuit to compare current states of the detection cells with initial states of the detection cells and to determine whether any of the detection cells have a current state that is different from their corresponding initial states; and a trigger circuit to trigger a refresh of the memory cells in the subject row based on a detection of detection cells in the subject row having current states that are different from their corresponding initial states.

Systems and methods for detecting a row hammer in a memory comprising a plurality of memory cells arranged in a plurality of rows may include: a plurality of detection cells in a subject row of memory cells, the detection cells to be set to respective initial states and configured to transition to a state different from their initial states in response to activations of memory cells in an adjacent row of memory cells; a comparison circuit to compare current states of the detection cells with initial states of the detection cells and to determine whether any of the detection cells have a current state that is different from their corresponding initial states; and a trigger circuit to trigger a refresh of the memory cells in the subject row based on a detection of detection cells in the subject row having current states that are different from their corresponding initial states.

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.

An operating method for a dynamic random access memory (DRAM) obtains a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus. Each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank. The method further combines the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address; and obtains an access command via the command bus.

A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.