A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first gate conductor layer partially surrounds a side surface of the semiconductor base material, and the second gate conductor layer entirely surrounds the side surface of the semiconductor base material.

Systems, apparatuses, and methods related to hierarchical memory are described. A hierarchical memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. Logic circuitry can be configured to determine that a request to access a persistent memory device corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device. Access data and control messages can be transferred between or within a memory device, including to or from a multiplexer and/or a state machine. A state machine can include logic circuitry configured to transfer interrupt request messages to and receive interrupt request messages.

Systems, apparatuses, and methods related to hierarchical memory are described. A hierarchical memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. Logic circuitry can be configured to determine that a request to access a persistent memory device corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device. Access data and control messages can be transferred between or within a memory device, including to or from a multiplexer and/or a state machine. A state machine can include logic circuitry configured to transfer interrupt request messages to and receive interrupt request messages.

Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.

Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

In a dynamic flash memory cell including: a HfO.sub.2 layer and a TiN layer surrounding a lower portion of a Si pillar standing on a P-layer substrate; a HfO.sub.2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N.sup.+ layers connected to a bottom portion and a top portion of the Si pillar, and an SGT transistor including: a SiO.sub.2 layer surrounding a lower portion of a Si pillar standing on the same P-layer substrate; a HfO.sub.2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N.sup.+ layers sandwiching the HfO.sub.2 layer in a perpendicular direction and connected to a top portion and a middle portion of the Si pillar, bottom positions of the Si pillar and the Si pillar are at the same position A. A bottom portion of an upper transistor portion of the dynamic flash memory cell composed of the HfO.sub.2 layer and the TiN layer in an upper portion of the Si pillar, and a bottom portion of an SGT transistor portion composed of the HfO.sub.2 layer and the TiN layer in an upper portion of the Si pillar are at the same position B.

In a dynamic flash memory cell including: a HfO.sub.2 layer and a TiN layer surrounding a lower portion of a Si pillar standing on a P-layer substrate; a HfO.sub.2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N.sup.+ layers connected to a bottom portion and a top portion of the Si pillar, and an SGT transistor including: a SiO.sub.2 layer surrounding a lower portion of a Si pillar standing on the same P-layer substrate; a HfO.sub.2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N.sup.+ layers sandwiching the HfO.sub.2 layer in a perpendicular direction and connected to a top portion and a middle portion of the Si pillar, bottom positions of the Si pillar and the Si pillar are at the same position A. A bottom portion of an upper transistor portion of the dynamic flash memory cell composed of the HfO.sub.2 layer and the TiN layer in an upper portion of the Si pillar, and a bottom portion of an SGT transistor portion composed of the HfO.sub.2 layer and the TiN layer in an upper portion of the Si pillar are at the same position B.

A first semiconductor layer 1 is formed on a substrate, a first impurity layer 3 and a second impurity layer 4 extending in a vertical direction are sequentially disposed on part of the first semiconductor layer 1, their sidewalls and the semiconductor layer 1 are covered by a second gate insulating layer 2, a gate conductor layer 22 and a second insulating layer are disposed in a groove formed there, and a second semiconductor layer 7, n.sup.+ layers 6a and 6c positioned at respective ends of the layer 7 and connected to a source line SL and a bit line BL, respectively, a second gate insulating layer 8 formed to cover the second semiconductor layer 7, and a second gate conductor layer 9 connected to a word line WL are disposed on the second impurity layer. Voltage applied to the source line SL, a plate line PL connected to the first gate conductor layer 22, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes in the channel region 12.