Example channel circuits, data storage devices, and methods for using a trained neural network to estimate the noise mixture in a read signal are described. Samples are determined from a digital read signal, such as the read signal from the non-volatile storage medium of a data storage device. The samples are processed through one or more instances of a neural network comprised of trained coefficients and outputting a set of estimate values for a noise mixture of the read signal. The set of estimate values may then be used to adjust parameters of the read channel for processing the read signal to detect and decode data.

Example channel circuits, data storage devices, and methods for using a trained neural network to estimate the noise mixture in a read signal are described. Samples are determined from a digital read signal, such as the read signal from the non-volatile storage medium of a data storage device. The samples are processed through one or more instances of a neural network comprised of trained coefficients and outputting a set of estimate values for a noise mixture of the read signal. The set of estimate values may then be used to adjust parameters of the read channel for processing the read signal to detect and decode data.

A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

A semiconductor integrated circuit according to an embodiment includes: a first memory bank that performing a read operation and outputting first data in accordance with a first clock signal; a second memory bank performing a read operation and outputting second data in accordance with the first clock signal; a configurable decoder supplying address information to the first and second memory banks; and an output module reconfigurable in one of a first and second modes, the first mode including a function of holding the first and second data in accordance with the first clock signal, and selecting and outputting the first data or the second data in accordance with a second clock signal having a frequency at least twice higher than the first clock signal, the second mode including a function of selecting and outputting the first data or the second data in accordance with the first clock signal.

A semiconductor integrated circuit according to an embodiment includes: a first memory bank that performing a read operation and outputting first data in accordance with a first clock signal; a second memory bank performing a read operation and outputting second data in accordance with the first clock signal; a configurable decoder supplying address information to the first and second memory banks; and an output module reconfigurable in one of a first and second modes, the first mode including a function of holding the first and second data in accordance with the first clock signal, and selecting and outputting the first data or the second data in accordance with a second clock signal having a frequency at least twice higher than the first clock signal, the second mode including a function of selecting and outputting the first data or the second data in accordance with the first clock signal.