A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.

Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.

Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.

The present disclosure provides a memory array. The memory array includes a first memory cell, a first word line, a second word line, a first bit line, a first complementary bit line, a second bit line, a second complementary bit line, a first sense amplifier, a second sense amplifier and a first logic circuit. When the memory array operates in a binary content-addressable memory (BCAM) mode, during a search operation, a first logic output indicates whether a logic level of the first word line matches a first logic value at a first terminal of a first data storage of the first memory cell, and whether a logic level of the second word line matches a first complementary logic value at a second terminal of the first data storage of the first memory cell.

A memory device includes a pair of memory cells, an analog-to-digital converter (ADC), and a processing circuit. The pair of memory cells has a first memory cell and a second memory cell. The ADC, having a first input terminal and a second input terminal, is configured to convert a first data signal at the first input terminal and a second data signal at the second input terminal into a digital output indicating a data value associated with a particular state stored in the pair of memory cells. The processing circuit, coupled to a storage node of the first memory cell, a storage node of the second memory cell, and the first and the second input terminals, is configured to selectively adjust the first data signal and the second data signal according to first data stored in the first memory cell and second data stored in the second memory cell.

The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

A display device includes a display substrate and a backplane substrate. The display substrate includes an array of micro-LEDs forming individual pixels. The backplane substrate includes a plurality of pixel logic hardware modules. Each pixel logic hardware module includes a local memory element configured to store a multi-bit pixel intensity value of a corresponding micro-LED for an image frame. The backplane substrate is bonded to a backside of the display substrate such that the pixel logic hardware modules are physically aligned behind the array of micro-LEDs and each pixel logic hardware module is electrically connected to a micro-LED of the corresponding pixel.

A processing apparatus having a programmable circuit including a plurality of ALUs, comprises a holding unit which holds configuration information for switching the programmable circuit from a first circuit setting to a second circuit setting, and timing information; and an updating unit which updates each ALU so as to switch the programmable circuit from the first circuit setting to the second circuit setting, wherein in switching from the first circuit setting to the second circuit setting after the programmable circuit has executed the first data processing, the updating unit, using the timing information, updates the first ALU at a timing at which last data of the first data processing is output from the first ALU, and updates the second ALU at a timing at which the last data is output from the second ALU.

A static random-access memory (SRAM) circuit and associated read operation method and write operation method are provided. The SRAM circuit includes memory units arranged in M columns and N rows, M bit lines, N row-voltage selection lines, N word lines, and a control circuit. The control circuit includes a controller, a voltage source, a voltage selection module, a word-line driving module, and a bit-line driving module. The voltage source provides a first voltage and a second voltage. When the control circuit performs access to the memory unit located in the mth column and the nth row, the voltage selection module transmits one of the first voltage and the second voltage to an nth row-voltage selection line. The voltage selection module transmits the second voltage to the other (N-1) row-voltage selection lines. The variables M, N, m, and n are positive integers.