A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.

Bandgap reference circuitry comprises a first current mirror connected to a power supply line and configured to supply a first current to a first node and a second current to a second node virtually-shorted to the first node, a first pn junction element between the first node and a ground line; a first variable resistor element between the second node and the ground line, and a second pn junction element connected in series to the first variable resistor element. The first variable resistor element has a resistance dependent on a power supply voltage supplied to the power supply line.

A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.

An environmental sensor implementing a sleep mode timer with an oscillator circuit suitable for low power applications is presented. The oscillator circuit includes a plurality of timer stages cascaded in series with each other. Each timer circuit includes a plurality of transistors and operates to output two voltages with opposite polarities, such that the polarities of the two voltages oscillate periodically based on leakage current in the plurality of transistors. Each timer circuit further includes one or more tuning transistors that operate to adjust a frequency at which the polarities of the voltages oscillate. A complementary-to-absolute temperature (CTAT) voltage generator is configured to receive a regulated voltage and supply a bias voltage to the one or more tuning transistors in each of the plurality of timer circuits, where the CTAT voltage generator adjusts the bias voltage linearly and inversely with changes in temperature.

There is provided a reference voltage generator for providing an adaptive voltage. The reference voltage generator includes a steady current source and a PMOS transistor and an NMOS transistor cascaded to each other. A reference voltage provided by the reference voltage generator is determined by gate-source voltages of the PMOS transistor and the NMOS transistor. As said gate-source voltages vary with the temperature and manufacturing process, the reference voltage forms a self-adaptive voltage.

A reference voltage generator circuit includes: a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled with each other and are located on a substrate, wherein the first transistor has a first conduction threshold voltage and a first rated voltage, wherein the second transistor has a second conduction threshold voltage and a second rated voltage, wherein the first rated voltage is higher than the second rated voltage; wherein the reference voltage generator circuit is configured to generate a bandgap reference voltage with temperature compensation according to a difference between the first conduction threshold voltage and the second conduction threshold voltage.

A circuit including a first PMOS (p-channel metal oxide semiconductor) transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, a second PMOS transistor, and a second NMOS transistor. A source, a gate, and a drain of the first PMOS transistor connect to a first node, a second node, and a third node, respectively. A source, a gate, and a drain of the first NMOS transistor connect to a fourth node, the third node, and the second node, respectively. A source, a gate, and a drain of the second PMOS transistor connect to the third node, the fourth node, and the second node, respectively. Finally, a source, a gate, and a drain of the second NMOS transistor connect to the second node, the first node, and the third node, respectively.

A voltage generation circuit having a temperature compensation function includes a first voltage generation circuit, a second voltage generation circuit, an output voltage control circuit, and a voltage selection circuit. The first voltage generation circuit is configured to generate a first voltage having a zero temperature coefficient, determined in response to a first control signal. The second voltage generation circuit is configured to generate a second voltage having a positive temperature coefficient, determined in response to a second control signal. The output voltage control circuit is configured to control an output of one of the first voltage and the second voltage in response to an operating mode. The voltage selection circuit is configured to select the first voltage or the second voltage in response to the output voltage control circuit.

Systems, methods, and apparatus for practical realization of a current source with a programmable temperature profile are described. The temperature profile can include profile segments with different programmable slopes. Programmable slopes of any one of the profile segments can be according to any of a ZTAT, PTAT and CTAT profiles. When integrated in an electronic device, the programmable temperature profile can be used statically with a pre-programmed configuration and optionally fused profile, or dynamically to control a performance of the electronic device via adjustments of the temperature profile.

There is provided a reference voltage generator for providing an adaptive voltage. The reference voltage generator includes a steady current source and a PMOS transistor and an NMOS transistor cascaded to each other. A reference voltage provided by the reference voltage generator is determined by gate-source voltages of the PMOS transistor and the NMOS transistor. As said gate-source voltages vary with the temperature and manufacturing process, the reference voltage forms a self-adaptive voltage.