Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.

Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

A reference generator system can include a PTAT circuit coupled to a signal supply node and configured to provide a voltage reference signal or a current reference signal that is based on a physical characteristic of one or more components of the PTAT circuit and a correction signal. The system can include a CTAT circuit coupled to the PTAT circuit and configured to provide the correction signal to the PTAT circuit. In an example, the reference generator system can be implemented at least in part using NMOS devices that comprise a portion of an indium gallium zinc oxide (IGZO) substrate.

Provided is a device connected to a clock and data signal lines, comprising: a voltage input unit configured to be inputted with a clock signal as an input signal from the clock signal line and to generate first reference voltage corresponding to a high level of the clock signal; a reference voltage generation unit configured to be inputted with predetermined input voltage and to generate second reference voltage; a voltage regulation unit for generating regulation voltage by using the second reference voltage to convert a level of the first reference voltage; a drive unit for stepping down the regulation voltage to generate output voltage; a control unit; and an output unit connected with the control unit, the drive unit, and the data signal line, for outputting the output voltage to the data signal line in response to input of a high level of a control signal from the control unit.

A reference generator system can include a PTAT circuit coupled to a signal supply node and configured to provide a voltage reference signal or a current reference signal that is based on a physical characteristic of one or more components of the PTAT circuit and a correction signal. The system can include a CTAT circuit coupled to the PTAT circuit and configured to provide the correction signal to the PTAT circuit. In an example, the reference generator system can be implemented at least in part using NMOS devices that comprise a portion of an indium gallium zinc oxide (IGZO) substrate.

An electronic circuit is disclosed. The electronic circuit includes a reference voltage generator, which includes a first candidate circuit configured to generate a first candidate reference voltage, a second candidate circuit configured to generate a second candidate reference voltage, and a selector circuit configured to select one of the first and second candidate reference voltages. The reference voltage generator also includes a third circuit configured to generate a power supply voltage based on the selected candidate reference voltage.

A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed. Also, a logic circuit comprising: a low voltage logic input; a high supply voltage input; a circuit ground voltage input; a high voltage output; a first tail device made from a first semiconductor material; and a second tail device made from a second different semiconductor material; wherein the first and second tail devices are coupled, in series, between the high voltage output and the circuit ground voltage input; and wherein respective gates of the first and second tail devices are coupled, in parallel, to the low voltage logic input.

Certain aspects of the present disclosure generally relate a regulator. For example, the regulator may include a control stage, a sense capacitor having first and second terminals, the first terminal coupled to an output of the voltage regulator, and a current amplifier having an input coupled to the second terminal of the sense capacitor and an output coupled to the control stage. The control stage of the regulator may adjust the output voltage of the regulator based at least in part on a current generated by the current amplifier.

In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Systems, methods, circuits, and apparatus including computer-readable mediums for managing bit line voltage generating circuits in memory devices are provided. An example bit line voltage generating circuit is configured to provide a stable clamping voltage to at least one bit line connecting memory cells in the memory device. The bit line voltage generating circuit includes an operational amplifier configured to receive a reference voltage, a feedback voltage, and a compensation current and output an output voltage, and an output transistor configured to provide a terminal voltage as the feedback voltage and the output voltage as a target voltage that is associated with the clamping voltage. The operational amplifier is configured to be unbalanced such that the terminal voltage is smaller than the reference voltage, and the compensation current is configured to compensate the operational amplifier such that the clamping voltage is substantially constant and independent from PVT (Process-Voltage-Temperature) effect.