A reference signal generator includes a voltage reference, an amplifier coupled to the voltage reference, and a precharge circuit coupled to the amplifier. The voltage reference is configured to generate a constant voltage. The amplifier is configured to receive the constant voltage from the voltage reference and generate a regulating primary output signal and a non-regulating secondary output signal. The precharge circuit is configured to charge a noise reduction capacitor with the non-regulating secondary output signal.

In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

A first transistor and a second transistor have control terminals coupled to each other. A current mirror circuit supplies a current having the same amount as that of a current I.sub.ref flowing through a first path including the second transistor to a second path including the first transistor and supplies a current having a predetermined number of times m of a current amount of the current I.sub.ref of the first path to a third path separate from the second path. The third transistor and a fourth transistor are provided on the third path. The third transistor has a source coupled to one end of the first transistor, and the fourth transistor has a gate coupled to a gate of the third transistor. A resistor is provided between a source of the fourth transistor and one end of the second transistor.

Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

Systems and methods are provided for generating a stable reference current that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners. In an example implementation, an improved reference current generator circuit is provided that includes a first circuit generating a first current that is proportional to absolute temperature and a second circuit generating a second current that is complementary to absolute temperature based on first transistors operating in respective triode regions. The second current compensates for process, voltage, and temperature variations in the first current at a node. According to some examples, the second current is also generated based on second transistors operating in respective saturation regions. The first current may be generated using a forward biased PN junction diode.

A low dropout (LDO) regulator includes: one or more power transistors configured to dispose between an input node and an output node, wherein the input node is a node to which an input voltage is applied and the output node is a node from which an output voltage is output; a voltage comparing unit configured to generate a comparative signal based on a difference between the output voltage and a first reference voltage; a digital control unit configured to generate a control signal for gating of the one or more power transistors in response to the comparative signal; and a gate driving unit configured to output a gating signal for the one or more power transistors in response to the control signal, wherein the gating signal is corresponding to one of the input voltage and a negative of the input voltage.

A voltage supervisor includes a first transistor coupled between a first supply voltage and a second supply voltage. The voltage supervisor includes a second transistor coupled between the first supply voltage and the second supply voltage. The voltage supervisor is configured to provide a first current proportional to a difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is also configured to provide a second current proportional to a difference in the first supply voltage and the difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is configured to compare the first current to the second current to determine a voltage value that changes a state responsive to the first supply voltage crossing a threshold.

In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

A voltage supervisor includes a first transistor coupled between a first supply voltage and a second supply voltage. The voltage supervisor includes a second transistor coupled between the first supply voltage and the second supply voltage. The voltage supervisor is configured to provide a first current proportional to a difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is also configured to provide a second current proportional to a difference in the first supply voltage and the difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is configured to compare the first current to the second current to determine a voltage value that changes a state responsive to the first supply voltage crossing a threshold.