A reference signal generator includes a voltage reference, an amplifier coupled to the voltage reference, and a precharge circuit coupled to the amplifier. The voltage reference is configured to generate a constant voltage. The amplifier is configured to receive the constant voltage from the voltage reference and generate a regulating primary output signal and a non-regulating secondary output signal. The precharge circuit is configured to charge a noise reduction capacitor with the non-regulating secondary output signal.

According to an aspect, a low-dropout (LDO) regulator includes a pre-charge buffer, an output stage, and a noise filter connected between the pre-charge buffer and the output stage of the LDO regulator. The noise filter includes a first resistor. The LDO regulator includes a transistor configured as an input to the output stage, and a compensation circuit connected to an input of the pre-charge buffer. The compensation circuit includes a second resistor. The compensation circuit is configured to provide a compensation current that produces a first voltage drop across the second resistor, where the first voltage drop offsets a second voltage drop produced by an input current of the transistor across the first resistor.

A power supply circuit, its generating and control methods are presented, relating to smart wearable devices. The power supply circuit comprises a Bandgap voltage reference, a real-time detection and control circuit, and a substitute voltage source. The real-time detection and control circuit is connected to the Bandgap voltage reference and the substitute voltage source, and adjusts an output voltage of the substitute voltage source to match an output voltage of the Bandgap voltage reference. After these output voltages are equal, the output voltage of the power supply circuit is provided by the substitute voltage source, and the Bandgap voltage reference can be disconnected from the circuit. This circuit can lower the power consumption of the Bandgap voltage reference without affecting the stability of the voltage output.

Voltage reference circuits are provided. A voltage reference circuit includes a first transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. The first transistor is formed by a plurality of second transistors. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of each second transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of each second transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.

Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a MOS transistor including a floating gate, a MOS transistor including a floating gate, and a MOS transistor including a floating gate.

According to embodiments, a semiconductor device includes a first switching element in which a first reference voltage is input to a gate; a second switching element in which a first voltage is input to a gate; a third switching element to which the first switching element is in Darlington connection; a fourth switching element to which the second switching element is in Darlington connection; a first current mirror circuit to regulate currents flowing in the third and fourth switching elements; a fifth switching element switched between ON and OFF states based on a difference between the first reference and the first voltages; a constant current circuit; a second current mirror circuit; and a voltage setting resistance element between a source of the first switching element and a gate of the third switching element or between a source of the second switching element and a gate of the fourth switching element.

According to embodiments, a semiconductor device includes a first switching element in which a first reference voltage is input to a gate; a second switching element in which a first voltage is input to a gate; a third switching element to which the first switching element is in Darlington connection; a fourth switching element to which the second switching element is in Darlington connection; a first current mirror circuit to regulate currents flowing in the third and fourth switching elements; a fifth switching element switched between ON and OFF states based on a difference between the first reference and the first voltages; a constant current circuit; a second current mirror circuit; and a voltage setting resistance element between a source of the first switching element and a gate of the third switching element or between a source of the second switching element and a gate of the fourth switching element.

A system may include a charge pump configured to boost an input voltage of the charge pump to an output voltage greater than the input voltage and a controller configured to control an output power of the charge pump to ensure that an input current of the charge pump is maintained below a current limit.

In described examples, a voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. A source of the third transistor is coupled to a source of the second transistor, and a gate and drain of the third transistor is coupled to gates of the first and second transistors and a first terminal of the current source. A drain of the fourth transistor is coupled to a drain of the first transistor and an input of the latch. A source of the fifth transistor is coupled to a source of the fourth transistor and the second terminal of the current source. A gate and drain of the fifth transistor is coupled to a gate of the fourth transistor and a drain of the second transistor.