A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

A second display region has a lower pixel density than a first display region. A third metal layer is located upper than a first metal layer and a second metal layer. The occupancy of the third metal layer in the second display region is lower than the occupancy in the first display region. In a pixel unit, the first metal layer includes a first electrode region to control an amount of electric current in a driving transistor, the second metal layer includes a second electrode region and a third electrode region to supply current to the driving transistor, and the third metal layer includes a main region to form a capacitor included in a capacitive element to store a control voltage for the driving transistor, and an island region surrounded by the main region with a gap and interconnected with a lower electrode region by a via region.

A display device includes: a display panel including pixels, a data driving circuit, a scan driving circuit which drives a plurality of first scan lines and a plurality of second scan lines, and a driving controller which controls the data driving circuit and the scan driving circuit to drive a first display area of the display panel at a first operating frequency and drive a second display area of the display panel at a second operating frequency lower than the first operating frequency while an operating mode is a multi-frequency mode. During the multi-frequency mode, first scan signals provided to first scan lines, which correspond to the second display area, of the plurality of first scan lines are maintained at inactive levels in predetermined frames, and second scan signals provided to the plurality of second scan lines transition to active levels at least twice in each of the predetermined frames.

A display device includes a pixel unit including first pixels disposed in a first area and second pixels disposed in a second area, an emission driver configured to sequentially supply emission signals of a turn-off level to the first pixels and the second pixels based on a first start signal, a first clock signal, and a second clock signal, and a first scan driver configured to sequentially supply first scan signals of a turn-on level to the first pixels based on a second start signal, the first clock signal, and the second clock signal, and sequentially supply the first scan signals of the turn-on level to the second pixels based on a third start signal, the first clock signal, and the second clock signal.

A display manufacturing system includes: a plurality of display devices, each including a display panel which displays an image; a driving voltage measurer which calculates a saturation voltage corresponding to a luminance of the image displayed on the display panel by changing a driving power voltage for driving the display panel; and a processor which calculates a current density and a degradation weight value based on the saturation voltage, and controls the display panel included in each of the plurality of display devices based on the current density and the degradation weight value.

A display apparatus includes a display panel including: a pixel array in which pixels including a plurality of light-emitting elements are arranged in a plurality of row lines and sub-pixel circuits provided for each of the plurality of light-emitting elements and providing a driving current to the light-emitting elements. The display apparatus also includes a drive unit is configured to: set image data voltages to the sub-pixel circuits of the display panel in a row line order during a data setting period for each row line; and drive the sub-pixel circuits to provide the driving current to the light-emitting elements of the pixel array in the row line order based on a sweep signal sweeping from a first voltage to a second voltage and the set image data voltages during a light-emitting period for each row line.

A display device includes a display panel, a display driver integrated circuit and a driving control circuit. The display panel includes a plurality of pixels connected to a plurality of driving lines and a plurality of source lines. The display driver integrated circuit includes a driving control signal generator. The driving control signal generator generates a driving control signal based on display device information and pixel values corresponding to at least a portion of the plurality of rows among a plurality of previous pixel values of a previous frame and a plurality of present pixel values of a present frame. The driving control circuit selectively connects the display driver integrated circuit with each of the plurality of driving lines based on the driving control signal such that first driving signals provided to first driving lines among the plurality of driving lines are blocked.

Embodiments of the present disclosure provide a driving board, a display panel and a display device. The driving board includes a plurality of pixel regions; the pixel regions each include a pixel circuit, a first power supply structure and a second power supply structure; the first power supply structure is configured to provide a first power voltage and the second power supply structure is configured to provide a second power voltage; the driving board includes a substrate, the pixel circuit, the first power supply structure and the second power supply structure are located at a same side of the substrate; wherein at least one of the first power supply structure and the second power supply structure includes a block structure, at least one inorganic layer is provided at a side of the block structure away from the substrate; and the block structure includes a first block structure, the first block structure includes at least one first opening. The present disclosure can reduce the chance of display anomalies.

A display device includes: a data driver for supplying a data signal to output lines; a demultiplexer connected to each of the output lines, the demultiplexer to supply the data signal supplied to each output line to a first data line and a second data line; first pixels disposed in a (2j−1)-th column and a (2k−1)-th row, the first pixels being connected to the first data line, wherein j and k are positive integers; second pixels disposed in the (2j−1)-th column and a (2k)-th row, the second pixels being connected to the second data line; third pixels disposed in a (2j)-th column and the (2k−1)-th row, the third pixels being connected to the first data line; and fourth pixels disposed in the (2j)-th column and the (2k)-th row, the fourth pixels being connected to the second data line.

A display device includes a first pixel driver connected to a sweep line, the first pixel driver generating a control current based on a first data voltage, a second pixel driver connected to a scan control line, the second pixel driver generating a driving current based on a second data voltage and controlling a period for which the driving current flows, based on the control current, and a light-emitting element connected to the second pixel driver to receive the driving current. The first pixel driver includes a first transistor generating the control current based on the first data voltage, a second transistor providing the first data voltage to a first electrode of the first transistor based on a scan write signal, and a first capacitor including a first capacitor electrode connected to a gate electrode of the first transistor, and a second capacitor electrode connected to the sweep line.