A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.

A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.

A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.

A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

Various aspects include methods and devices for implementing the methods for error checking a memory system. Aspects may include receiving, from a row buffer of a memory, access data corresponding to a column address of a memory access, in which the row buffer has data of an activation unit of the memory corresponding to a row address of the memory access, determining multiple error correction codes (ECCs) for the access data using the column address, and checking the access data for an error utilizing at least one of the multiple ECCs. In some aspects, the multiple ECCs may include a first ECC having data from an access unit of the memory corresponding with the column address, and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.

Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.

Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.

Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.