A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.

Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.

An amplification circuit includes: a sense amplification circuit including a read node, a complementary read node, a first node and a second node; an isolation circuit, which couples the read node to a bit line and couples the complementary read node to a complementary bit line in a sense amplification stage; an offset cancellation circuit, which couples the bit line to the complementary read node and couple the complementary bit line to read node in an offset cancellation stage; and a first power supply circuit, coupled to the first node, including a first power supply and a second power supply, a power supply voltage of the first power supply being higher than that of the second power supply, the first power supply circuit couples the first power supply to the first node in offset cancellation stage, and couples the second power supply to the first node in sense amplification stage.

An amplification circuit includes: a sense amplification circuit including a read node, a complementary read node, a first node and a second node; an isolation circuit, which couples the read node to a bit line and couples the complementary read node to a complementary bit line in a sense amplification stage; an offset cancellation circuit, which couples the bit line to the complementary read node and couple the complementary bit line to read node in an offset cancellation stage; and a first power supply circuit, coupled to the first node, including a first power supply and a second power supply, a power supply voltage of the first power supply being higher than that of the second power supply, the first power supply circuit couples the first power supply to the first node in offset cancellation stage, and couples the second power supply to the first node in sense amplification stage.

A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.

A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.

A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

A memory device for data searching and a data searching method thereof are provided. The data searching method includes the following steps. A searching word is received and then divided into a plurality of sections. The sections are encoded as a plurality of encoded sections, so that the encoded sections may correspond to a plurality of memory blocks in a memory array. The encoded sections are directed into the memory blocks to perform data comparisons and obtaining a respective result of data comparison. Thereafter, addresses of bit lines which match the searching word are obtained according to respective result of data comparison for each of memory block.