A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

A control amplifying circuit includes a power supply output circuit, an isolation control circuit and an amplifying circuit. The power supply output circuit is configured to receive a power supply switching signal, and select one preset voltage value from at least two preset voltage values according to the power supply switching signal to output as a preset power supply signal. The isolation control circuit is configured to receive a control command signal and the preset power supply signal, and generate an isolation control signal according to the control command signal. The amplifying circuit is configured to receive the isolation control signal and a signal to be processed, and amplify the signal to be processed based on the isolation control signal to obtain a target amplified signal.

A control amplifying circuit includes a power supply output circuit, an isolation control circuit and an amplifying circuit. The power supply output circuit is configured to receive a power supply switching signal, and select one preset voltage value from at least two preset voltage values according to the power supply switching signal to output as a preset power supply signal. The isolation control circuit is configured to receive a control command signal and the preset power supply signal, and generate an isolation control signal according to the control command signal. The amplifying circuit is configured to receive the isolation control signal and a signal to be processed, and amplify the signal to be processed based on the isolation control signal to obtain a target amplified signal.

The present disclosure relates to the field of semiconductor circuit design, and in particular, to a readout circuit layout, including: a first PMOS layout, configured to form a first PMOS transistor <P1>, wherein a source of the first PMOS transistor is connected to a first signal terminal, and the first signal terminal is configured to receive a first level signal; a first NMOS layout, configured to form a first NMOS transistor <N1>, wherein a source of the first NMOS transistor is connected to a second signal terminal, and the second signal terminal is configured to receive a second level signal; a gate of the first PMOS transistor <P1> and a gate of the first NMOS transistor <N1> are connected to a bit line, and a drain of the first PMOS transistor <P1> and a drain of the first NMOS transistor <N1> are connected to a complementary readout bit line.

The present disclosure relates to the field of semiconductor circuit design, and in particular, to a readout circuit layout, including: a first PMOS layout, configured to form a first PMOS transistor <P1>, wherein a source of the first PMOS transistor is connected to a first signal terminal, and the first signal terminal is configured to receive a first level signal; a first NMOS layout, configured to form a first NMOS transistor <N1>, wherein a source of the first NMOS transistor is connected to a second signal terminal, and the second signal terminal is configured to receive a second level signal; a gate of the first PMOS transistor <P1> and a gate of the first NMOS transistor <N1> are connected to a bit line, and a drain of the first PMOS transistor <P1> and a drain of the first NMOS transistor <N1> are connected to a complementary readout bit line.

A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.