A device includes a multiplication unit and a configurable summing unit. The multiplication unit is configured to receive data and weights for an Nth layer, where N is a positive integer. The multiplication unit is configured to multiply the data by the weights to provide multiplication results. The configurable summing unit is configured by Nth layer values to receive an Nth layer number of inputs and perform an Nth layer number of additions, and to sum the multiplication results and provide a configurable summing unit output.

A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

A memory device for data searching and a data searching method thereof are provided. The data searching method includes the following steps. A searching word is received and then divided into a plurality of sections. The sections are encoded as a plurality of encoded sections, so that the encoded sections may correspond to a plurality of memory blocks in a memory array. The encoded sections are directed into the memory blocks to perform data comparisons and obtaining a respective result of data comparison. Thereafter, addresses of bit lines which match the searching word are obtained according to respective result of data comparison for each of memory block.

A memory device for data searching and a data searching method thereof are provided. The data searching method includes the following steps. A searching word is received and then divided into a plurality of sections. The sections are encoded as a plurality of encoded sections, so that the encoded sections may correspond to a plurality of memory blocks in a memory array. The encoded sections are directed into the memory blocks to perform data comparisons and obtaining a respective result of data comparison. Thereafter, addresses of bit lines which match the searching word are obtained according to respective result of data comparison for each of memory block.

Methods, systems, and devices related to an improved driver for non-binary signaling are described. A driver for a signal line may include a set of drivers of a first type and a set of drivers of a second type. When the driver drives the signal line using multiple drivers of the first type, at least one additional driver of the first type may compensate for non-linearities associated with one or more other drivers of the first type, which may have been calibrated at other voltages. The at least one additional driver of the first type may be calibrated for use at a particular voltage, to compensate for non-linearities associated with the one or more other drivers of the first type as exhibited at that particular voltage.

A method and device for testing a memory and a method for simulated testing include operations as follows. First data is written into a to-be-tested storage unit through a Sense Amplifier (SA), second data different from the first data is written into the storage unit through the SA, and an amplification duration of the SA is shortened during the writing the second data, and data stored in the storage unit is read, and whether the storage unit is abnormal is determined according to the read data.

A method and device for testing a memory and a method for simulated testing include operations as follows. First data is written into a to-be-tested storage unit through a Sense Amplifier (SA), second data different from the first data is written into the storage unit through the SA, and an amplification duration of the SA is shortened during the writing the second data, and data stored in the storage unit is read, and whether the storage unit is abnormal is determined according to the read data.

A local amplifier circuit includes write control transistors, configured to connect, based on write enable signal, global data line to local data line; column selection transistors, configured to connect, based on column selection signal, bit line to local data line; first control PMOS transistor having gate connected to local data line, one of source or drain connected to global data line, and the other one connected to read control transistor; and second control PMOS transistor having gate connected to complementary local data line, one of source or drain connected to complementary global data line, and the other one connected to read control transistor. Read control transistors are configured to pull up or down levels at terminals of first control PMOS transistor and second control PMOS transistor, each of which is source or drain connected to a respective one of read control transistors, to preset level based on read enable signal.

A local amplifier circuit includes write control transistors, configured to connect, based on write enable signal, global data line to local data line; column selection transistors, configured to connect, based on column selection signal, bit line to local data line; first control PMOS transistor having gate connected to local data line, one of source or drain connected to global data line, and the other one connected to read control transistor; and second control PMOS transistor having gate connected to complementary local data line, one of source or drain connected to complementary global data line, and the other one connected to read control transistor. Read control transistors are configured to pull up or down levels at terminals of first control PMOS transistor and second control PMOS transistor, each of which is source or drain connected to a respective one of read control transistors, to preset level based on read enable signal.