A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to V.sub.ref with decoding information generated during the decoding process.

Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to V.sub.ref with decoding information generated during the decoding process.

A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.

A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.

A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.

A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.

A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M−1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M−1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M−1) reference voltages, At least two sense amplifiers of the (M−1) sense amplifiers have different sensing characteristics.

A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M−1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M−1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M−1) reference voltages, At least two sense amplifiers of the (M−1) sense amplifiers have different sensing characteristics.