An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

A pixel and an organic light emitting diode (OLED) display using the pixel are disclosed. The pixel includes a driving transistor for transmitting a driving current, an OLED configured to receive a first portion of the driving current and a bypass transistor configured to receive a second portion of the driving current.

A pixel and an organic light emitting diode (OLED) display using the pixel are disclosed. The pixel includes a driving transistor for transmitting a driving current, an OLED configured to receive a first portion of the driving current and a bypass transistor configured to receive a second portion of the driving current.

Provided is a scanning-line driving circuit configured with a plurality of unit circuits cascaded in stages and integrally formed with a display panel. The unit circuit includes a first transistor, a resistor, a second transistor, and an output transistor. The first transistor has a first conductive electrode supplied with a first-level voltage and a second conductive electrode connected to a first node. The resistor is connected to the first node at a first terminal. The second transistor has a first conductive electrode supplied with a second-level voltage and a second conductive electrode connected to a second terminal of the resistor. The output transistor has a control electrode connected to the first node and a first conductive electrode connected to an output terminal. The resistor is formed in a semiconductor layer. The unit circuit further includes an upper electrode formed above the resistor. This configuration allows the scanning-line driving circuit to prevent an operation failure due to a change in characteristics of the resistor in the unit circuit.

Provided is a scanning-line driving circuit configured with a plurality of unit circuits cascaded in stages and integrally formed with a display panel. The unit circuit includes a first transistor, a resistor, a second transistor, and an output transistor. The first transistor has a first conductive electrode supplied with a first-level voltage and a second conductive electrode connected to a first node. The resistor is connected to the first node at a first terminal. The second transistor has a first conductive electrode supplied with a second-level voltage and a second conductive electrode connected to a second terminal of the resistor. The output transistor has a control electrode connected to the first node and a first conductive electrode connected to an output terminal. The resistor is formed in a semiconductor layer. The unit circuit further includes an upper electrode formed above the resistor. This configuration allows the scanning-line driving circuit to prevent an operation failure due to a change in characteristics of the resistor in the unit circuit.

A display panel and a display device are provided. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data-writing module, a driving module including a driving transistor, and a compensation module. The driving transistor includes a source, a gate, an active layer, a first drain and a second drain, and is divided into first and second driving portions having channel regions with lengths of L1 and L2, respectively. The data-writing module is connected to the source, the compensation module is connected between the gate and the first drain, and L2/L1ΔVsd2/(ΔVsg+V0)−1, 0V0ΔVgd2×½; alternatively, the data-writing module is connected to the first drain, the compensation module is connected between the gate and the second drain, and L1/L2ΔVsd2/(ΔVgd2+V0)−1, 0V0ΔVsg×½.

Provided is a device for controlling luminance of a display, having a simplified ACL circuit compared to the prior art. The device for controlling luminance of a display calculates the average luminance (Y_avg) when video data is input, and determines the luminance variation (ΔY) according to the average luminance. The device for controlling luminance of a display may adjust the luminance of a display by controlling a current (driving current) that is used to drive a light-emitting diode included in a pixel, instead of modifying video data for the adjustment of luminance. That is, unlike the prior art, the device for controlling luminance of a display does not modify video data, for the control of luminance.

Provided is a device for controlling luminance of a display, having a simplified ACL circuit compared to the prior art. The device for controlling luminance of a display calculates the average luminance (Y_avg) when video data is input, and determines the luminance variation (ΔY) according to the average luminance. The device for controlling luminance of a display may adjust the luminance of a display by controlling a current (driving current) that is used to drive a light-emitting diode included in a pixel, instead of modifying video data for the adjustment of luminance. That is, unlike the prior art, the device for controlling luminance of a display does not modify video data, for the control of luminance.

A display device, a gate drive circuit, a shift register and a control method are disclosed. The shift register includes a first shift register unit and a second shift register unit, the first shift register unit is configured to write a first control signal to the first node, and write a first clock signal to the first signal output terminal under control of a voltage of the first node; the second shift register unit is configured to write a second clock signal to the second signal output terminal under control of the voltage of the first node; during time of a frame, the first clock signal and a first input signal provided by a first signal input terminal are pulse signals, and the second clock signal is a DC signal.

The present disclosure discloses a pixel circuit and a drive method thereof, and a display panel. The pixel circuit includes a drive transistor, a first light-emission control sub-circuit, a second light-emission control sub-circuit, a first threshold compensation sub-circuit, a second threshold compensation sub-circuit, a first initialization sub-circuit, a second initialization sub-circuit, a data-in sub-circuit, a capacitor, and a light-emitting element; wherein the second light-emission control sub-circuit is connected to the first light-emission control sub-circuit, a second initialization sub-circuit and a gate of the drive transistor, and is configured to send the signal of the first threshold compensation sub-circuit or the signal of the second threshold compensation sub-circuit to the gate of the drive transistor.