A sulfurization detection resistor makes it possible to detect a degree of sulfurization accurately and easily, and a manufacturing method for such sulfurization detection resistor. A sulfurization detection resistor includes an insulated substrate having a rectangular parallelepiped shape, a first front electrode and a second front electrode formed at both ends on a main surface of the insulated substrate, multiple sulfurization detecting conductors connected in parallel to the first front electrode, multiple resistive elements connected between the sulfurization detecting conductors and the second front electrode, and a protective film formed to partially cover the sulfurization detecting conductors and entirely cover the resistive elements. The sulfurization detecting conductors have their sulfurization detecting portions exposed out of the protective film, and different timings are set for these sulfurization detecting portions respectively to become disconnected depending on a cumulative amount of sulfurization.

Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode. The one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device.

In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

Provided is a shunt resistor including: a first terminal and a second terminal each made of an electrically conductive metal material and having a first plane, a second plane, and an outer peripheral surface around the planes; and a resistive body connected to the respective first planes and connecting the first terminal and the second terminal, the first planes of the first terminal and the second terminal opposing each other. A bonding area between the resistive body and the first planes is smaller than an area of the first planes. The first terminal and the second terminal each have a hole penetrating through from the first plane to the second plane. A voltage detection terminal is connected to opposing surface sides of the first terminal and the second terminal.

The input device includes an insulating layer, a plurality of first resistors arrayed on one side of the insulating layer with a longitudinal direction thereof extending in a first direction, a plurality of second resistors arrayed on an opposite side of the insulating layer with a longitudinal direction thereof extending in a second direction intersecting the first direction, and a pair of electrodes provided at opposite ends of a corresponding one of the first resistors and the second resistors, wherein upon the first resistors and/or the second resistors being pressed, a resistance value between the pair of electrodes associated with pressed one or more of the first resistors and the second resistors changes continuously in accordance with a magnitude of applied pressure.

The input device includes an insulating layer, a plurality of first resistors arrayed on one side of the insulating layer with a longitudinal direction thereof extending in a first direction, a plurality of second resistors arrayed on an opposite side of the insulating layer with a longitudinal direction thereof extending in a second direction intersecting the first direction, and a pair of electrodes provided at opposite ends of a corresponding one of the first resistors and the second resistors, wherein upon the first resistors and/or the second resistors being pressed, a resistance value between the pair of electrodes associated with pressed one or more of the first resistors and the second resistors changes continuously in accordance with a magnitude of applied pressure.

Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode. The one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device.

A method of forming a resistor circuit, the method comprising forming a first resistor comprising a first type of resistor, forming a second resistor comprising a second type of resistor, the first type of resistor being different from the second type of resistor and simultaneously doping a first part of the first resistor and a second part of the second resistor, the first resistor and the second resistor being configured such that doping of the first part of the first resistor and the second part of the second resistor defines a temperature coefficient of the first resistor and a temperature coefficient of the second resistor, wherein the temperature coefficient of the first resistor and the temperature coefficient of the second resistor have opposite signs.

A method of forming a resistor circuit, the method comprising forming a first resistor comprising a first type of resistor, forming a second resistor comprising a second type of resistor, the first type of resistor being different from the second type of resistor and simultaneously doping a first part of the first resistor and a second part of the second resistor, the first resistor and the second resistor being configured such that doping of the first part of the first resistor and the second part of the second resistor defines a temperature coefficient of the first resistor and a temperature coefficient of the second resistor, wherein the temperature coefficient of the first resistor and the temperature coefficient of the second resistor have opposite signs.