An electrical component having a layered structure including first and second electrodes each having first and second electrode portions located in a plane and at least partially embedded in a dielectric body, each of the first and second electrode portions separated by a gap and substantially isolated by the dielectric, the first electrode substantially parallel to and at least partially overlapping the second electrode, wherein the first and second electrodes are electrically isolated and separated by the dielectric body.

A varistor includes an effective layer having first and second surfaces opposite to each other, a first ineffective layer stacked on the first surface of the effective layer, a second ineffective layer stacked on the second surface of the effective layer, and an external electrode. The effective layer includes a ceramic layer having a polycrystalline structure including crystal particles exhibiting voltage nonlinear characteristics, and internal electrodes stacked alternately on the ceramic layer. The thickness of the second ineffective layer is equal to or more than 1.1 times a thickness of the first ineffective layer and equal to or smaller than 6 times the thickness of the first ineffective layer. This varistor has a small size and excellent surge resistance.

A laminated varistor includes a varistor layer, a first internal electrode provided on an upper surface of the varistor layer, a second internal electrode provided on a lower surface of the varistor layer and facing the first internal electrode across the varistor layer in upward and downward directions, a first external electrode provided on a first side surface of the varistor layer and electrically connected to the first internal electrode, and a second external electrode provided on a second side surface of the varistor layer and electrically connected to the second internal electrode. The first internal electrode is extended from the first external electrode in a first extension direction. The first internal electrode includes first electrode strips arranged in a first arrangement direction perpendicular to the first extension direction and spaced apart from one another. This laminated varistor has improved surge-resistant characteristics.

A laminated varistor includes a varistor layer, a first internal electrode provided on an upper surface of the varistor layer, a second internal electrode provided on a lower surface of the varistor layer and facing the first internal electrode across the varistor layer in upward and downward directions, a first external electrode provided on a first side surface of the varistor layer and electrically connected to the first internal electrode, and a second external electrode provided on a second side surface of the varistor layer and electrically connected to the second internal electrode. The first internal electrode is extended from the first external electrode in a first extension direction. The first internal electrode includes first electrode strips arranged in a first arrangement direction perpendicular to the first extension direction and spaced apart from one another. This laminated varistor has improved surge-resistant characteristics.

In a multilayer ceramic electronic component, a first auxiliary electrode layer spaced away from a second internal electrode layer and exposed to a first end surface is on a same plane as a ceramic layer on which the second internal electrode layer is located, a second auxiliary electrode layer spaced away from a first internal electrode layer and exposed to a second end surface is on a same plane as the ceramic layer on which the first internal electrode layer is located, a first via conductor is at a central portion in a width direction of the first internal electrode layer and the first auxiliary electrode layer and exposed to the first end surface, and a second via conductor is at a central portion in a width direction of the second internal electrode layer and the second auxiliary electrode layer and exposed to the second end surface.

In a multilayer ceramic electronic component, a first auxiliary electrode layer spaced away from a second internal electrode layer and exposed to a first end surface is on a same plane as a ceramic layer on which the second internal electrode layer is located, a second auxiliary electrode layer spaced away from a first internal electrode layer and exposed to a second end surface is on a same plane as the ceramic layer on which the first internal electrode layer is located, a first via conductor is at a central portion in a width direction of the first internal electrode layer and the first auxiliary electrode layer and exposed to the first end surface, and a second via conductor is at a central portion in a width direction of the second internal electrode layer and the second auxiliary electrode layer and exposed to the second end surface.

In an embodiment a sensor device includes a sensor chip having a plurality of printed ceramic layers and unprinted ceramic layers, at least one termination layer configured to make electrical contact with an electrically conductive material, wherein the termination layer is formed at least on a top side and/or on a bottom side of the sensor chip, wherein the printed ceramic layers are at least partially printed with an electrically conductive material, and wherein an electrical resistance of the sensor chip is determined by an overlap area of the electrically conductive material or by a distance of the electrically conductive material from the termination layer and at least one damping layer directly located at at least a partial area of an outer surface of the sensor chip, wherein the damping layer includes a material which has a greater elasticity than a material of the termination layer.

In an embodiment a sensor device includes a sensor chip having a plurality of printed ceramic layers and unprinted ceramic layers, at least one termination layer configured to make electrical contact with an electrically conductive material, wherein the termination layer is formed at least on a top side and/or on a bottom side of the sensor chip, wherein the printed ceramic layers are at least partially printed with an electrically conductive material, and wherein an electrical resistance of the sensor chip is determined by an overlap area of the electrically conductive material or by a distance of the electrically conductive material from the termination layer and at least one damping layer directly located at at least a partial area of an outer surface of the sensor chip, wherein the damping layer includes a material which has a greater elasticity than a material of the termination layer.

A complex device is provided. A complex device according to an embodiment of the present invention comprises: a suppressor including a pair of first dielectric sheet layers having a first dielectric constant and a pair of internal electrodes spaced apart from each other on one surface of one of the pair of first dielectric sheet layers; a capacitor including a plurality of second dielectric sheet layers having a second dielectric constant and a plurality of capacitor electrodes provided on each of the plurality of second dielectric sheet layers; and a pair of external terminals provided on both sides of the suppressor and the capacitor to be connected to the plurality of capacitor electrodes and the pair of internal electrodes. Here, provided is the complex device in which the first dielectric constant is greater than the second dielectric constant.

A chip resistor includes a substrate, a first electrode, a second electrode, a first resistor body, a second resistor body, and a connection electrode. The substrate includes a first primary surface. The first electrode includes a first terminal electrode and a first auxiliary electrode. The second electrode includes a second terminal electrode and a second auxiliary electrode. The first auxiliary electrode has a larger area than the first terminal electrode and the second auxiliary electrode has a larger area than the second terminal electrode, in plan view of the first primary surface of the substrate.