A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T≥2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2≤X≤T, wherein, for each value of X in the range 1≤X<T: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.

A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T≥2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2≤X≤T, wherein, for each value of X in the range 1≤X<T: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.

A quench protection arrangement for a superconducting magnet is disclosed. The arrangement comprises: a superconducting magnet comprising a plurality of magnet sections; a plurality of varistors, wherein each of the plurality of varistors is electrically connected in parallel across a respective one of the plurality of magnet sections; and a heater arrangement electrically connected to the plurality of varistors and configured to apply heat to each of the plurality of magnet sections in response to a change in a voltage across any one or more of the plurality of varistors. A method of protecting a superconducting magnet is also disclosed.

A resistor assembly can be used in a tap changer. The resistor assembly may include: a resistor element, which is held by at least two resistor holders; a base plate with at least one opening and on which the at least two resistor holders holding the resistor element are arranged; a plurality of guides, respectively formed in each of the resistor holders and being configured to position a first end and a second end of the resistor element with respect to a longitudinal direction between the two resistor holders; and contact points of the resistor element, the contact points being electrically contacted by contacts of the tap changer in a condition where the resistor element is inserted into the resistor holder.

A resistor assembly can be used in a tap changer. The resistor assembly may include: a resistor element, which is held by at least two resistor holders; a base plate with at least one opening and on which the at least two resistor holders holding the resistor element are arranged; a plurality of guides, respectively formed in each of the resistor holders and being configured to position a first end and a second end of the resistor element with respect to a longitudinal direction between the two resistor holders; and contact points of the resistor element, the contact points being electrically contacted by contacts of the tap changer in a condition where the resistor element is inserted into the resistor holder.

A high voltage resistor arrangement has a rod-shaped supporting substrate made of electrically insulating material and a plurality of individual resistors and/or discrete capacitors spaced apart from each other in the longitudinal direction of the supporting substrate, wherein at least one conductive path extending in the longitudinal direction of the supporting substrate is formed on the supporting substrate which is galvanically connected to the individual resistors and/or discrete capacitors, and wherein the individual resistors and/or discrete capacitors are realized as SMD components soldered directly onto the supporting substrate by means of solder pads.

A high voltage resistor arrangement has a rod-shaped supporting substrate made of electrically insulating material and a plurality of individual resistors and/or discrete capacitors spaced apart from each other in the longitudinal direction of the supporting substrate, wherein at least one conductive path extending in the longitudinal direction of the supporting substrate is formed on the supporting substrate which is galvanically connected to the individual resistors and/or discrete capacitors, and wherein the individual resistors and/or discrete capacitors are realized as SMD components soldered directly onto the supporting substrate by means of solder pads.

An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2.sup.X−1, each having a resistance equal to R*(2.sup.Y)*i, i being an index having a value ranging from 1 to 2.sup.X−1, a first of the M resistors having a resistance of R*2.sup.Y, a last of the M resistors having a resistance of R*2.sup.Y*(2.sup.X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.