H01J2237/002

Ultra high purity conditions for atomic scale processing

An apparatus for atomic scale processing is provided. The apparatus may include a reactor (100) and an inductively coupled plasma source (10). The reactor may have inner (154) and outer surfaces (152) such that a portion of the inner surfaces define an internal volume (156) of the reactor. The internal volume of the reactor may contain a fixture assembly (158) to support a substrate (118) wherein the partial pressure of each background impurity within the internal volume may be below 10.sup.−6 Torr to reduce the role of said impurities in surface reactions during atomic scale processing.

Electrostatic chucks with coolant gas zones and corresponding groove and monopolar electrostatic clamping electrode patterns

An electrostatic chuck for a substrate processing system is provided and includes a baseplate, an intermediate layer disposed on the baseplate, and a top plate. The top plate is bonded to the baseplate via the intermediate layer and is configured to electrostatically clamp to a substrate. The top plate includes a monopolar clamping electrode and seals. The monopolar clamping electrode includes a groove opening pattern with coolant gas groove opening sets. The seals separate coolant gas zones. The coolant gas zones include four or more coolant gas zones. Each of the coolant gas zones includes distinct coolant gas groove sets. The top plate includes the distinct coolant gas groove sets. Each of the distinct coolant gas groove sets has one or more coolant gas supply holes and corresponds to a respective one of the coolant gas groove opening sets.

HIGH TEMPERATURE DETACHABLE VERY HIGH FREQUENCY (VHF) ELECTROSTATIC CHUCK (ESC) FOR PVD CHAMBER

Embodiments of substrate supports for use in substrate processing chambers are provided herein. In some embodiments, a substrate support includes: an upper assembly having a base plate assembly coupled to a lower surface of a cooling plate, wherein the base plate assembly includes a plurality of electrical feedthroughs, and wherein the cooling plate includes a plurality of openings aligned with the plurality of electrical feedthroughs; an electrostatic chuck disposed on the upper assembly and removably coupled to the cooling plate, wherein the electrostatic chuck has a chucking electrode disposed therein that is electrically coupled to a first pair of electrical feedthroughs of the plurality of electrical feedthroughs; and an inner tube coupled to the cooling plate and configured to provide an RF delivery path to the electrostatic chuck.

ETCHING METHOD, SEMICONDUCTOR MANUFACTURING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

An etching method according to one embodiment, includes alternately switching a first step and a second step. The first step introduces a first gas containing a fluorine atom without supplying radiofrequency voltage to form a surface layer on a surface of a target cooled at a temperature equal to or lower than a liquefaction temperature of the first gas. The second step introduces a second gas gaseous at the first temperature and different from the first gas, and supplies the radiofrequency voltage, to generate plasma from the second gas to etch the target by sputtering using the plasma.

Ultrahigh selective nitride etch to form FinFET devices

A substrate processing system for selectively etching a layer on a substrate includes an upper chamber region, an inductive coil arranged around the upper chamber region and a lower chamber region including a substrate support to support a substrate. A gas distribution device is arranged between the upper chamber region and the lower chamber region and includes a plate with a plurality of holes. A cooling plenum cools the gas distribution device and a purge gas plenum directs purge gas into the lower chamber. A surface to volume ratio of the holes is greater than or equal to 4. A controller selectively supplies an etch gas mixture to the upper chamber and a purge gas to the purge gas plenum and strikes plasma in the upper chamber to selectively etch a layer of the substrate relative to at least one other exposed layer of the substrate.

WAFER PLACEMENT TABLE

A wafer placement table is a wafer placement table that includes a refrigerant flow channel through which refrigerant is flowed and includes a top base including a ceramic base incorporating an electrode and having a wafer placement surface on a top surface of the ceramic base, a bottom base on a top surface of which a flow channel groove defining a side wall and a bottom of the refrigerant flow channel is provided, and a seal member disposed between the top base and the bottom base so as to seal the refrigerant flow channel from an outside.

Magnetron assembly having coolant guide for enhanced target cooling

Embodiments of coolant guides for use in magnetron assemblies are provided herein. In some embodiments, a coolant guide for use in a magnetron assembly includes: a body having a guide channel extending through the body, wherein an upper opening of the guide channel corresponding with an upper surface of the body has a first size and a lower opening of the guide channel corresponding with a lower surface of the body has a second size greater than the first size, and wherein the body includes a first pair of outer sidewalls that are substantially parallel to each other and a second pair of outer sidewalls that are angled toward each other; and an upper lip extending away from an upper surface of the body.

SORPTION CHAMBER WALLS FOR SEMICONDUCTOR EQUIPMENT
20220319821 · 2022-10-06 ·

A sorption structure defined in a plasma process chamber includes an inner layer having one or more heating elements to heat the sorption structure, a middle section having a coolant flow delivery network through which a coolant circulates to cool the sorption structure to a temperature to allow selective adsorption of by-products released in the process chamber, and a vacuum flow network that is connected to a vacuum line to create low pressure vacuum and remove the by-products released from the sorption structure. A lattice structure is defined over the middle section, the lattice structure includes network of openings defined in a plurality of layers to increase surface area for improved by-products adsorption. The inner section is disposed adjacent to the middle section. An outer layer of the lattice structure faces an interior region of the chamber. The openings in the layers of the lattice structure progressively increase in size from the inner layer to the outer layer, such that the outer layer provides a larger surface area for adsorbing the by-products. The vacuum line is activated during adsorption step to create a low pressure region in the lattice structure relative to a pressure in the chamber so as to adsorb the by-products. Desorption step is performed in conjunction with WAC/CWAC to reliably remove the accumulated by-products from the sorption wall.

UPPER ELECTRODE ASSEMBLY

An upper electrode assembly used in a plasma processing apparatus is provided. The upper electrode assembly comprises: an electrode plate; a metal plate; and a heat transfer sheet disposed between the electrode plate and the metal plate and having a vertically oriented portion. The vertically oriented portion has a plurality of vertically oriented graphene structures oriented along a vertical direction.

Method of low-temperature plasma generation, method of an electrically conductive or ferromagnetic tube coating using pulsed plasma and corresponding devices

The present invention resides in the unifying idea of synchronizing a positive voltage pulse supplied to an electrically conductive or ferromagnetic tube and a exciting negative voltage pulse on a hollow cathode induced on the background of a high-frequency capacitive discharge. In one embodiment, the invention relates to a method of generating low-temperature plasma in a vacuum chamber comprising a hollow cathode and an electrode, the method comprising the step of igniting the pulsed DC discharge in the hollow cathode wherein the positive voltage pulse at least partially overlaps with the negative voltage pulse, and the positive voltage pulse at least partially overlaps with the negative voltage pulse on the hollow cathode. In another embodiment, the present invention relates to a method of coating the inner walls of hollow tubes which utilizes the above-mentioned low-temperature plasma generation process. In another embodiment, the invention relates to a low-temperature plasma generating device comprising a hollow cathode located in the vacuum chamber, a RF plasma source, a pulse DC burst source, and a bipolar pulse source. In another embodiment, an object of the invention is an apparatus adapted to coat the inner sides of hollow tubes comprising a low-temperature plasma generating device.