Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.

An integrated circuit (IC) device includes a first-fin-type active region, a second-fin-type active region, and an inter-region stepped portion. The first-fin-type active region protrudes from a substrate in a first region of the substrate and has a first width in a first direction. The second-fin-type active region protrudes from the substrate in a second region of the substrate and has a second width in the first direction. The second width is less than the first width. The inter-region stepped portion is formed at an interface between the first region and the second region on a bottom surface, which is a portion of the substrate between the first-fin-type active region and the second-fin-type active region.

An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.

Provided are a method of manufacturing a thin film transistor, a dehydrogenating apparatus for performing the method, and an organic light emitting display device including a thin film transistor manufactured by the same. A method of manufacturing a thin film transistor includes reducing a content of oxygen in a chamber for performing a dehydrogenation process of an amorphous silicon layer from a first value to a second value, inserting a substrate on which the amorphous silicon layer is formed into the chamber, heating the inside of the chamber to perform the dehydrogenation process on the amorphous silicon layer, and forming a polysilicon layer by crystallizing the amorphous silicon layer using a laser.

The semiconductor device includes a semiconductor substrate, a plurality of source regions formed in a stripe shape on the semiconductor substrate, a plurality of gate electrodes formed in a stripe shape between a plurality of the stripe shaped source regions on the semiconductor substrate, an insulating film for covering the source regions and the gate electrodes, the insulating film including a contact hole for partly exposing the source regions in a part of a predetermined region with respect to a longitudinal direction of the source regions; and a source electrode formed on the insulating film and electrically connected to the source region via the contact hole.

Short-wave infrared (SWIR) focal plane arrays (FPAs) comprising a Si layer through which light detectable by the FPA reaches photodiodes of the FPA, at least one germanium (Ge) layer including a plurality of distinct photosensitive areas including at least one photosensitive area in each of a plurality of photosensitive photosites, each of the distinct photosensitive areas comprising a plurality of proximate steep structures of Ge having height of at least 0.5 μm and a height-to-width ratio of at least 2, and methods for forming same.

A semiconductor package including a semiconductor chip having an active surface and a non-active surface opposite to the active surface, a ground member disposed on the active surface of the semiconductor chip, and an electromagnetic shielding member passing through the semiconductor chip, electrically connected to the ground member, and covering at least some regions of the non-active surface of the semiconductor chip may be provided.

A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.