A silicon-on-insulator radio frequency device and a silicon-on-insulator substrate are provided. In the silicon-on-insulator radio frequency device, a pit is formed on a surface of a high resistivity silicon plate which is close to a buried oxide layer. The pit may be filled with an insulating material, thereby increasing an equivalent surface resistance of the high resistivity silicon plate; or no insulating material is filled into the pit, that is, the pit remains a vacuum state or is only filled with air, which can increase the equivalent surface resistance of the high resistivity silicon plate as well. In such, an eddy current generated on a surface of the high resistivity silicon plate under the action of a radio frequency signal may be reduced. As a result, loss of the radio frequency signal is reduced and the linearity of the radio frequency signal is improved.

Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.

Methods, systems, devices and apparatus for use in screening and/or selecting a library of nucleic acid molecules and/or nucleic acid tagged or encoded molecules for binding to or interaction with a target molecule or substance (e.g., for use in new compound or drug discovery) are described. In some embodiments the device comprises: (a) a spatially addressable array, said array comprising a plurality of separate and discrete locations thereon; (b) a plurality of different oligomers operably connected to said spatially addressable array at different ones of said separate and discrete locations; (c) a tag sequence which is complementary to, and is hybridized to, each of said oligomers; and (d) a candidate chemical operably connected to each of said tag sequences, wherein each of said discrete locations is a unique identifier for its corresponding oligomer; and wherein said tag sequence is a unique identifier for its connected candidate chemical.

A semiconductor device including a first fin active area substantially parallel to a second fin active area, a first source/drain in the first fin active area, a second source/drain in the second fin active area, a first contact plug on the first source/drain, and a second contact plug on the second source/drain. The center of the second contact plug is offset from the center of the second source/drain.

An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.

An IC device includes a simultaneously formed capacitor and resistor structure. The capacitor and resistor may be located between a Back End of the Line (BEOL) interconnect stack and an external device interconnect pad of the IC device. The resistor may be used to step down a voltage applied across the resistor. The resistor may include one or more resistor plates that are formed simultaneously with a respective one or more plates of the capacitor. For example, a capacitor plate and a resistor plate may be patterned and formed from the same conductive sheet. Each of the resistor plates may be connected to one or more vertical interconnect accesses (VIA).

A semiconductor device including: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof.

In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area MC defined by a peripheral isolation region 3c. The memory cell area MC has multiple cell active regions k defined by multiple cell isolation regions 3a, 3b. Guard active regions GLa, GLb made of the semiconductor substrate are disposed in the border between the memory cell area MC and the peripheral isolation region 3c to separate the memory cell isolation regions 3a, 3b from the peripheral isolation region 3c.