A semiconductor package includes a semiconductor die, an encapsulation encapsulating the semiconductor die, the encapsulation having a first side and an opposing second side, a plurality of contact pads for electrically contacting the semiconductor die, the contact pads being arranged on the first side of the encapsulation, and a plurality of inspection holes arranged in communication with the contact pads and extending from the first side to the second side, such that solder joints on the first side of the encapsulation are optically inspectable using the inspection holes viewed from the second side of the encapsulation.

A pick and place LED testing apparatus, comprising: a test station operative in use to power a group of LEDs; a bondhead operative in use to pick said group of LEDs from a source wafer and place said group of LEDs on said test station for testing; and an optical sensor operative in use to measure an optical characteristic of said group of LEDs when tested, wherein at least a portion of said bondhead is translucent to provide an optical path from said group of LEDs to said optical sensor.

A semiconductor substrate processing apparatus includes: a metastructure layer divided into a plurality of microstructures by grooves, a light-transmitting dielectric substrate that supports the plurality of microstructures and is configured to allow an electromagnetic wave to be transmitted therethrough, and a frame including an exhaust hole configured to receive gas introduced from the grooves such as to provide suction force to the semiconductor substrate, wherein each of the plurality of microstructures has a smaller width than a wavelength of the electromagnetic wave, and each of the grooves has a smaller width than the wavelength of the electromagnetic wave.

A measurement apparatus includes: an input part into which a signal according to a state of a measurement target is input; a measurement part configured to measure the state of the measurement target from the signal input to the input part, and generate, when the measurement of the state of the measurement target is completed, a switching instruction signal instructing switching a multiplexer configured to selectively output the signal; and an output part configured to output the switching instruction signal generated by the measurement part.

The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.

In an embodiment, a method for evaluating a surface of a semiconductor substrate includes directing an incident light beam having multiple wavelengths at a position of a layer having a surface profile configured to form an optical diffraction grating, the layer including a Group III nitride, detecting a reflected beam, reflected from the position, and obtaining a spectrum of reflected intensity as a function of wavelength, the spectrum being representative of the surface profile of the position of the layer from which the beam is reflected, comparing the spectrum obtained from the detected beam with one or more reference spectra stored in memory, and estimating at least one parameter of the surface profile.

The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.

A first mask with a first pattern is formed above a substrate, a first portion is formed in or above the substrate using the first mask, a second mask with a second pattern is formed above the substrate, a first positional deviation between the first portion and the second pattern is measured, a second portion is formed in or above the substrate using the second mask, a third mask with a third pattern is formed above the substrate, and a third portion is formed in or above the substrate using the third mask. In the forming the third mask, the third pattern is formed in a material film for the third mask with alignment in consideration of the first positional deviation.

When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

Test key structures, integrated circuit packages and methods of forming the same are disclosed. One of the test key structures includes a first pattern over a polymer layer, and at least one second pattern covering the first pattern. Besides, the second pattern and the first pattern have substantially the same outer profile, one of the first pattern and the second pattern includes a dielectric material and the other of the first pattern and the second pattern includes a metal material.