An electronic control device includes a board including a heat sink on which a heat generation element is mounted, and a housing that is in contact with the board and dissipates heat of the heat generation element to the outside. A potential of the housing is a ground, and a potential of the heat sink is a non-ground. The board includes a first layer including a first non-ground wiring that is in direct contact with the heat sink, and a second layer including a second ground wiring that is in electrical and thermal contact with the housing. The first non-ground wiring and the second ground wiring overlap each other in plan view from a thickness direction of the board.

Provided are a glass composition capable of sealing through low-temperature firing without containing environmentally harmful lead, and a sealing material using the same. The glass composition includes, in terms of mol %, 1%, to 30% of MgO+CaO+SrO+BaO+ZnO, 30% to 80% of TeO.sub.2, and 5% to 30% of MoO.sub.3.

A sensor device includes a sensor element, a supporting member, a substrate, and a bonding wire. The supporting member is electrically connected to the sensor element. The substrate is electrically connected to the supporting member. The bonding wire forms at least part of a connection path that electrically connects the sensor element and the supporting member together. The substrate and an installation member on which the sensor element is installed intersect with each other. The sensor element and the supporting member are separated from each other.

A circuit board includes an interconnect and an insulating layer that covers the interconnect. The interconnect includes a first interconnect that is formed to serve as a recognition mark of which planar shape is a predetermined shape. The insulating layer has a through-hole of which planar shape is variant and that penetrates the insulating layer in a thickness direction of the insulating layer such that an entire upper surface of the first interconnect is exposed. The through-hole includes a first through-hole of which planar shape is a predetermined shape and that penetrates the insulating layer in the thickness direction such that the entire upper surface of the first interconnect is exposed and a second through-hole that serves as part of an inner wall surface of the first through-hole and that penetrates the insulating layer in the thickness direction.

A circuit board includes an interconnect and an insulating layer that covers the interconnect. The interconnect includes a first interconnect that is formed to serve as a recognition mark of which planar shape is a predetermined shape. The insulating layer has a through-hole of which planar shape is variant and that penetrates the insulating layer in a thickness direction of the insulating layer such that an entire upper surface of the first interconnect is exposed. The through-hole includes a first through-hole of which planar shape is a predetermined shape and that penetrates the insulating layer in the thickness direction such that the entire upper surface of the first interconnect is exposed and a second through-hole that serves as part of an inner wall surface of the first through-hole and that penetrates the insulating layer in the thickness direction.

An interposer includes a base layer having a first surface and a second surface, a redistribution structure on the first surface, an interposer protection layer on the second surface, a pad wiring layer on the interposer protection layer, an interposer through electrode passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the pad wiring layer, an interposer connection terminal attached to the pad wiring layer, and a wiring protection layer including a first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first to third portions have thicknesses different from each other.

A substrate having an electronic component embedded therein includes a core structure including a first insulating body and core wiring layers and having a cavity penetrating through a portion of the first insulating body, an electronic component disposed in the cavity, an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, a wiring layer disposed on the insulating material, and a build-up structure disposed on the insulating material and including a second insulating body and a build-up wiring layer. A material of the first insulating body has a coefficient of thermal expansion (CTE) less than a CTE of the second insulating body, and the insulating material has a CTE less than a CTE of a material of the second insulating body.

A device package and a method of forming a device package are described. The device package includes a dielectric on a conductive pad, and a first via on a first seed on a top surface of the conductive pad. The device package further includes a conductive trace on the dielectric, and a second via on a second seed layer on the dielectric. The conductive trace connects to the first via and the second via, where the second via connects to an edge of the conductive trace opposite from the first via. The dielectric may include a photoimageable dielectric or a buildup film. The device package may also include a seed on the dielectric prior to the conductive trace on the dielectric, and a second dielectric on the dielectric, the conductive trace, and the first and second vias, where the second dielectric exposes a top surface of the second via.

Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity.

Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity.