H01L23/16

Apparatus and system with package stiffening magnetic inductor core and methods of making the same

An apparatus includes a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to the substrate. One or more sections of the stiffener may includes a magnetic material. The apparatus further includes an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. In some examples where a first coil is wrapped around a first section of the stiffener, and a second coil is wrapped around a second section of the stiffener, current supplied to the first coil generates at the second coil a current that is further transmitted to the one or more semiconductor dies.

Apparatus and system with package stiffening magnetic inductor core and methods of making the same

An apparatus includes a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to the substrate. One or more sections of the stiffener may includes a magnetic material. The apparatus further includes an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. In some examples where a first coil is wrapped around a first section of the stiffener, and a second coil is wrapped around a second section of the stiffener, current supplied to the first coil generates at the second coil a current that is further transmitted to the one or more semiconductor dies.

Package structures and methods of forming the same

An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

Package structures and methods of forming the same

An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE
20220392859 · 2022-12-08 ·

A semiconductor device includes a semiconductor element layer including a semiconductor substrate including a bump area and a dummy bump area. A TSV structure is in the bump area and vertically extends through the semiconductor substrate, a first topmost line is in the bump area and on the TSV structure and electrically connected to the TSV structure, a signal bump is in the bump area and has a first width in a first direction and is electrically connected to the TSV structure via the first topmost line, a second topmost line is in the dummy bump area and has the same vertical level as a vertical level of the first topmost line and extends in the first direction, and a dummy bump is in the dummy bump area and contacts the second topmost line and has a second width in the first direction larger than the first width.

SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE
20220392859 · 2022-12-08 ·

A semiconductor device includes a semiconductor element layer including a semiconductor substrate including a bump area and a dummy bump area. A TSV structure is in the bump area and vertically extends through the semiconductor substrate, a first topmost line is in the bump area and on the TSV structure and electrically connected to the TSV structure, a signal bump is in the bump area and has a first width in a first direction and is electrically connected to the TSV structure via the first topmost line, a second topmost line is in the dummy bump area and has the same vertical level as a vertical level of the first topmost line and extends in the first direction, and a dummy bump is in the dummy bump area and contacts the second topmost line and has a second width in the first direction larger than the first width.

ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAME

An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.

ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAME

An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.

Unitary housing for electronic device

An electronic device having a unitary housing is disclosed. The device can include a first housing component having an open cavity, an internal electronic part disposed within the cavity, a second housing component disposed across the cavity, and a support feature disposed within the cavity and arranged to support the second housing component. The first housing component can be formed from metal, while the second housing component can be formed from a plurality of laminated foil metal layers. The second housing component can be attached to the first housing component via one or more ultrasonic welds, such that a fully enclosed housing is created. The fully enclosed housing can be hermetically sealed, and the outside surfaces thereof can be machined or otherwise finished after the ultrasonic welding.

High density interconnection using fanout interposer chiplet
11594494 · 2023-02-28 · ·

Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.