A 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. An internal cooling structure that includes the MIO layers provides double sided cooling for the first semiconductor device and the second semiconductor device.

A semiconductor device includes a semiconductor element having a surface on which a first electrode and a second electrode are disposed, a conductor plate having a surface facing the surface of the semiconductor element and electrically connected to the first electrode, an insulating layer disposed on the surface of the conductor plate and covers a part of the surface of the conductor plate, and a conductor circuit pattern disposed on the insulating layer. The conductor circuit pattern has at least one conductor line electrically connected to the semiconductor element. The at least one conductor line includes a conductor line electrically connected to the second electrode.

A semiconductor device includes a semiconductor element having a surface on which a first electrode and a second electrode are disposed, a conductor plate having a surface facing the surface of the semiconductor element and electrically connected to the first electrode, an insulating layer disposed on the surface of the conductor plate and covers a part of the surface of the conductor plate, and a conductor circuit pattern disposed on the insulating layer. The conductor circuit pattern has at least one conductor line electrically connected to the semiconductor element. The at least one conductor line includes a conductor line electrically connected to the second electrode.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.

The invention is notably directed to a transflective display device. The device comprises a set of pixels, wherein each of the pixels comprises a portion of bi-stable, phase change material, hereafter a PCM portion, having at least two reversibly switchable states, in which it has two different values of refractive index and/or optical absorption. The device further comprises one or more spacers, optically transmissive, and extending under PCM portions of the set of pixels. One or more reflectors extend under the one or more spacers. An energization structure is in thermal or electrical communication with the PCM portions, via the one or more spacers. Moreover, a display controller is configured to selectively energize, via the energization structure, PCM portions of the pixels, so as to reversibly switch a state of a PCM portion of any of the pixels from one of its reversibly switchable states to the other. A backlight unit is furthermore configured, in the device, to allow illumination of the PCM portions through the one or more spacers. The backlight unit is controlled by a backlight unit controller, which is configured for modulating one or more physical properties of light emitted from the backlight unit. The invention is further directed to related devices and methods of operation.

An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.

A metasurface unit cell for use in constructing a metasurface array is provided. The unit cell may include a ground plane layer comprising a first conductive material, and a phase change material layer operably coupled to the ground plane layer. The phase change material layer may include a phase change material configured to transition between an amorphous phase and a crystalline phase in response to a stimulus. The unit cell may further include a patterned element disposed adjacent to the phase change material layer and includes a second conductive material. In response to the phase change material transitioning from a first phase to a second phase, the metasurface unit cell may resonate to generate an electromagnetic signal having a defined wavelength. The first phase may be the amorphous phase or the crystalline phase and the second phase may be the other of the amorphous phase or the crystalline phase.

A metasurface unit cell for use in constructing a metasurface array is provided. The unit cell may include a ground plane layer comprising a first conductive material, and a phase change material layer operably coupled to the ground plane layer. The phase change material layer may include a phase change material configured to transition between an amorphous phase and a crystalline phase in response to a stimulus. The unit cell may further include a patterned element disposed adjacent to the phase change material layer and includes a second conductive material. In response to the phase change material transitioning from a first phase to a second phase, the metasurface unit cell may resonate to generate an electromagnetic signal having a defined wavelength. The first phase may be the amorphous phase or the crystalline phase and the second phase may be the other of the amorphous phase or the crystalline phase.

An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.