A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

A semiconductor device for testing a semiconductor wafer includes a circuit board, a probe disposed below the circuit board and facing the semiconductor wafer, an integrated substrate disposed between the circuit board and the probe, and signal-transmitting module disposed on the circuit board and next to the integrated substrate. The probe is electrically coupled to the circuit board through the integrated substrate, and the signal-transmitting module transmits a test signal to the probe through the integrated substrate and the circuit board to perform a test to the semiconductor wafer. Another semiconductor device including the integrated substrate and a manufacturing method thereof are provided.

Integrated circuit (IC) structures include transistor devices with interconnect structures, e.g., a source contact, drain contact, and/or gate contact. The interconnect structures have rounded top surfaces. Contouring the top surfaces of transistor contacts may decrease the likelihood of electrical shorting and may permit a larger volume of insulating dielectric between adjacent contacts.

A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.

A wiring board includes: a substrate having transparency; a plurality of first wirings which are arranged on an upper surface of the substrate and extend in a first direction and each of which has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface; and has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface. The first wiring has a pair of side surfaces which extend in the first direction and are adjacent to the back surface of the first wiring, and each of the pair of side surfaces of the second wiring is recessed inward. The second wiring has a pair of side surfaces which extend in the second direction and are adjacent to the back surface of the second wiring.

Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.