A device area and a marking area neighboring the device area over a dielectric stack are determined. The dielectric stack includes insulating material layers and sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area are patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer, and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area is greater than or equal to a second pattern density of the second marking sub-area. A photoresist layer is formed to cover the staircase pattern and expose the marking pattern, and the photoresist layer is trimmed to expose a portion of the dielectric stack along a horizontal direction. An etching process is performed to maintain the marking pattern and remove the exposed portion of the dielectric stack and form a staircase.

A device area and a marking area neighboring the device area over a dielectric stack are determined. The dielectric stack includes insulating material layers and sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area are patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer, and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area is greater than or equal to a second pattern density of the second marking sub-area. A photoresist layer is formed to cover the staircase pattern and expose the marking pattern, and the photoresist layer is trimmed to expose a portion of the dielectric stack along a horizontal direction. An etching process is performed to maintain the marking pattern and remove the exposed portion of the dielectric stack and form a staircase.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

The present invention relates to an improved electronic circuit, as well as an improved substrate with electronic circuits, with an identification pattern. The invention makes it possible to make them identifiable and amongst other things to retrace the circuit(s) in this way through the production process. Furthermore, the invention relates to an improved production method for circuits and substrates according to the invention.

The present invention relates to an improved electronic circuit, as well as an improved substrate with electronic circuits, with an identification pattern. The invention makes it possible to make them identifiable and amongst other things to retrace the circuit(s) in this way through the production process. Furthermore, the invention relates to an improved production method for circuits and substrates according to the invention.

A semiconductor device includes a chip, a first kerf adjacent the chip and having a first main direction, a second kerf adjacent the chip and having a second main direction. A kerf junction is formed by the first kerf and the second kerf. A crack stop barrier is located along a first portion of a perimeter of the kerf junction.

A semiconductor device includes a chip, a first kerf adjacent the chip and having a first main direction, a second kerf adjacent the chip and having a second main direction. A kerf junction is formed by the first kerf and the second kerf. A crack stop barrier is located along a first portion of a perimeter of the kerf junction.

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.