Disclosed is a strip substrate including a dielectric layer that has a plurality of unit regions spaced apart from each other in a first direction and a saw line region between the unit regions, a plurality of conductive dummy patterns on corresponding unit regions of the dielectric layer, a plurality of saw line patterns on the saw line region of the dielectric layer and extending in a second direction that intersects the first direction, and a protection pattern that covers the dielectric layer. Ends of the conductive dummy patterns are spaced apart from each other in a direction parallel to the first direction. Ends of the saw line patterns are spaced apart from each other in a direction parallel to the second direction. The protection pattern is between the ends of the conductive dummy patterns and between the ends of the saw line patterns.

Disclosed is a strip substrate including a dielectric layer that has a plurality of unit regions spaced apart from each other in a first direction and a saw line region between the unit regions, a plurality of conductive dummy patterns on corresponding unit regions of the dielectric layer, a plurality of saw line patterns on the saw line region of the dielectric layer and extending in a second direction that intersects the first direction, and a protection pattern that covers the dielectric layer. Ends of the conductive dummy patterns are spaced apart from each other in a direction parallel to the first direction. Ends of the saw line patterns are spaced apart from each other in a direction parallel to the second direction. The protection pattern is between the ends of the conductive dummy patterns and between the ends of the saw line patterns.

A semiconductor device capable of improving the quality of a pixel region, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device are to be provided. The present technology provides a semiconductor device that includes: a first substrate in which a pixel region including a pixel having a photoelectric conversion unit is formed; and a second substrate in which a logic circuit that processes a signal output from the pixel region is formed, the first substrate and the second substrate being stacked. In the semiconductor device, at least one of marks including a mark to be used in an exposure process during the manufacture of the semiconductor device and/or a mark to be used in an inspection process for the semiconductor device is formed in a first region that is a region between a first scribe region that is a peripheral portion of the first substrate and the pixel region and/or in a second region that is a region between a second scribe region that is a peripheral portion of the second substrate and a region corresponding to the pixel region in the second substrate.

A semiconductor device capable of improving the quality of a pixel region, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device are to be provided. The present technology provides a semiconductor device that includes: a first substrate in which a pixel region including a pixel having a photoelectric conversion unit is formed; and a second substrate in which a logic circuit that processes a signal output from the pixel region is formed, the first substrate and the second substrate being stacked. In the semiconductor device, at least one of marks including a mark to be used in an exposure process during the manufacture of the semiconductor device and/or a mark to be used in an inspection process for the semiconductor device is formed in a first region that is a region between a first scribe region that is a peripheral portion of the first substrate and the pixel region and/or in a second region that is a region between a second scribe region that is a peripheral portion of the second substrate and a region corresponding to the pixel region in the second substrate.

A method of manufacturing a bonded structure includes providing a first semiconductor structure including a first die, a first dielectric layer and a first conductive pad electrically connected to the first die and surrounded by the first dielectric layer; providing a second semiconductor structure including a second die, a second dielectric layer and a second conductive pad electrically connected to the second die and surrounded by the second dielectric layer; providing a carrying module including a holding unit configured to hold the second semiconductor structure and an anchoring unit movably attached to the holding unit, wherein the anchoring unit includes an end portion; disposing the carrying module and the second semiconductor structure over the first semiconductor structure; and displacing the anchoring unit towards the first semiconductor structure to make the end portion in contact with the first dielectric layer.

In a semiconductor device in a wafer state, an element region and a scribe region are defined in one main surface of a semiconductor substrate. In the element region, a vertical MOS transistor is formed as a semiconductor element. In the scribe region, an n-type column region and a p-type column region are defined. An n-type column resistor is formed in the n-type column region. A p-type column resistor is formed in the p-type column region.

In a semiconductor device in a wafer state, an element region and a scribe region are defined in one main surface of a semiconductor substrate. In the element region, a vertical MOS transistor is formed as a semiconductor element. In the scribe region, an n-type column region and a p-type column region are defined. An n-type column resistor is formed in the n-type column region. A p-type column resistor is formed in the p-type column region.

Provided is a semiconductor device including: a semiconductor substrate provided with an active portion and an edge termination structure portion surrounding the active portion; an interlayer dielectric film provided above the semiconductor substrate; a protective film provided above the interlayer dielectric film; and a protruding portion provided farther from the active portion than the edge termination structure portion and protruding further than the interlayer dielectric film. The protruding portion is not covered with the protective film. The protective film is provided closer to the active portion than the protruding portion.

Provided is a semiconductor device including: a semiconductor substrate provided with an active portion and an edge termination structure portion surrounding the active portion; an interlayer dielectric film provided above the semiconductor substrate; a protective film provided above the interlayer dielectric film; and a protruding portion provided farther from the active portion than the edge termination structure portion and protruding further than the interlayer dielectric film. The protruding portion is not covered with the protective film. The protective film is provided closer to the active portion than the protruding portion.

A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.