A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sublayers that are stacked on the semiconductor body. Each of the sublayers comprises a respective stress in one or more directions, where the respective stresses of at least two of the sublayers are different. The sublayers may include a first stressor sublayer comprising first stress, and a second stressor sublayer comprising a second stress that at least partially compensates for the first stress in the one or more directions. Related devices and methods of fabrication are also discussed.

In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.

A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes first and second sublayers of first and second oxide materials, respectively, where the first oxide material is different than the second oxide material. Related devices and fabrication methods are also discussed.

A semiconductor packaging structure includes: a substrate, a redistribution layer having one conductive plugs, metal bumps disposed on the redistribution layer, and electrically connected with the redistribution layer including the conductive plug; a semiconductor chip over the redistribution layer and aligned to and electrically connected with the conductive plug; an underfill layer filling a gap between the redistribution layer and the semiconductor chip and the conductive plugs; a polymer layer on the redistribution layer, over the plurality of metal bumps, the underfill layer and the semiconductor chip, exposing only top parts of the plurality of metal bumps and top part of the semiconductor chip; and an antenna module disposed on the second surface of the substrate.

A semiconductor substrate has a first surface and a second surface that includes an inner region and an outer region. The semiconductor substrate includes a drift layer of a first conductivity type and a terminal well region of a second conductivity type. The terminal well region includes a portion that extends from between the inner region and the outer region toward the outer region. A first electrode is on the first surface. A second electrode is on at least part of the inner region and electrically connected to the terminal well region, and has its edge located on a boundary between the inner region and the outer region. A peripheral structure is provided on part of the outer region, away from the second electrode. A surface protective film covers the edge of the second electrode and at least part of the outer region and has the peripheral structure engaged therein.

A silicon carbide semiconductor device includes an n-type epitaxial layer provided on a SiC substrate, a front surface electrode provided on the epitaxial layer, and a p-type electric field relieving region provided in the upper layer of the epitaxial layer in a terminal region. On the epitaxial layer, a first protective film composed of an interlayer insulating film and a protective oxide film that covers at least a part of the electric field relieving region is provided. A second protective film composed of a polyimide protective film is provided via a silicon nitride film so as to cover the outer end portion of the surface electrode, the first protective film, and at least a part of the epitaxial layer. The silicon nitride film protrudes from the second protective film at both an inner side end portion and an outer side end portion.

A device includes a die with a metallization stack. The device includes a substrate with a first region, a second region and a third region that underly the metallization stack and a first isolation trench filled with a polymer dielectric that extends between the first region and the second region of the substrate. The device also includes a second isolation trench filled with the polymer dielectric that extends between the second region and the third region. The polymer dielectric overlays a periphery of the substrate.

Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.