A self-destructing device includes a stressed substrate with a heater thermally coupled to the stressed substrate. The device includes a power source and trigger circuitry comprising a sensor and a switch. The sensor generates a trigger signal when exposed to a trigger stimulus. The switch couples the power source to the heater in response to the trigger signal When energized by the power source, the heater generates heat sufficient to initiate self-destruction of the stressed substrate.

A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.

The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

The present exemplary embodiments provide a security circuit which senses a micro probe attack by changing both ends of a wire of a shield to be a high impedance state to change a connection state of the wire and analyzing a test signal reflected by the connected wire path, or senses a focused ion beam attack by changing both ends of a wire of a shield to be a high impedance state to change a connection state of the wire and analyzing a test signal which passes through a selected wire for every group, or blocks a physical approach by changing an accessible signal path to be a high impedance state when an external attack is detected by the detection circuit.

A physical unclonable function (PUF) chip is provided. The physical unclonable function (PUF) chip includes a chip with a top metal connection layer, an array of spaced electrode plates on the top metal connection layer of the chip, a deposition layer, on the top metal connection layer between each two adjacent electrode plates. An opening is formed between the each two adjacent electrode plates in a row, and each two adjacent electrode plates are tangential to the opening formed between the two adjacent electrode plates. The physical unclonable function (PUF) chip further includes a conductive coating layer on the chip and the conductive coating layer includes conductive particles with randomly distributed size, and a package substrate, packaged with the chip including the conductive coating layer.

An electronic device, such as a dynamic transaction card having an EMV chip, that acts as a TPM having a memory, an applet, and a cryptographic coprocessor performs secure firmware and/or software updates, and performs firmware and/or software validation for firmware and/or software that is stored on the electronic device. Validation may compare a calculated checksum with a checksum stored in EMV chip memory. If a checksum calculated for firmware and/or a software application matches a checksum stored in EMV chip memory of the transaction card, the transaction card may operate normally. If a checksum calculated for firmware and/or a software application does not match a checksum stored in EMV chip memory of the transaction card, the transaction card may freeze all capabilities, erase the memory of the transaction card, display data indicative of a fraudulent or inactive transaction card, and/or the like.

An improved system and method for reading an upconversion response from nanoparticle inks is provided. A is adapted to direct a near-infrared excitation wavelength at a readable indicia, resulting in a near-infrared emission wavelength created by the upconverting nanoparticle inks. A short pass filter may filter the near-infrared excitation wavelength. A camera is in operable communication with the short pass filter and receives the near-infrared emission wavelength of the readable indicia. The system may further include an integrated circuit adapted to receive the near-infrared emission wavelength from the camera and generate a corresponding signal. A readable application may be in operable communication with the integrated circuit. The readable application receives the corresponding signal, manipulates the signal, decodes the signal into an output, and displays and/or stores the output.

A chip includes a metal layer, a portion of a first sawbow line, and a portion of a second sawbow line. The portion of the first sawbow line and the portion of the second sawbow line respectively correspond to the first sawbow line and the second sawbow line in a cut state. The portions of the first and second sawbow lines may be on different layers, and the metal layer may be arranged over the portion of the first sawbow line and/or the portion of the second sawbow line to hide at least one of the portions of the sawbow lines in the cut state.

A semiconductor die includes a circuit, a plurality of metal layers, a first sawbow line coupled to the circuit, and a second sawbow line coupled to the circuit. The first sawbow line is hidden under a first metal layer of the plurality of metal layers when the first sawbow line is in a cut state. The second sawbow line is hidden under the first metal layer or a second metal layer of the plurality of metal layers when the second sawbow line is in a cut state. The first sawbow line and the second sawbow line are on different ones of the plurality of metal layers. A number of pull-down or pull-up resistors may be included to set the logical states of the sawbow lines, in order to disable a predetermined mode of operation of the die when a wafer including the die is cut. The sawbow lines may carry a variety of types of signals (e.g., analog, digital, random, ground, supply) that makes the nature and value of them extremely hard to detect/hack.