Parts are exposed to liquid chromatography to generate a corresponding chromatogram, wherein the chromatogram is compared to a chromatogram of a genuine part to determine if the tested part is suspect counterfeit. Depending on the selected predetermined target analytes, the generated chromatogram can be used to assess an associated manufacturing process as conforming or non-conforming.

Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

A method for allowing a reflective layer to abut against an edge of a metal contact while preventing contamination of a metal contact for an LED die is provided. The method includes encapsulating an electrical contact (i.e. metal contact) via with a barrier layer prior to deposition of a reflective film layer. The barrier layer encapsulates the metal contact by defining a mask pattern with a larger size than the metal contact via, which prevents the metal contact from becoming contaminated by the reflective film. This encapsulation reduces contamination of the metal contact and also reduces the voltage drop during operation of the LED die.

An epitaxial base plate including a base plate body; a plurality of bosses arranged on the base plate body in an array; a plurality of contact electrodes correspondingly disposed on tops of the bosses; a planarization layer covering the bosses and a region of the base plate body without being covered by the bosses. The planarization layer defines a plurality of first through holes corresponding to the bosses to expose plurality of contact electrodes via the plurality of first through holes; and a plurality of pads arranged on the planarization layer in an array and electrically connected to the corresponding contact electrodes via the first through holes. An area of a vertical projection of the pad on the base plate body is greater than an area of a vertical projection of the contact electrode on the base plate body.

Embodiments herein describe providing a decoupling capacitor on a first wafer (or substrate) that is then bonded to a second wafer to form an integrated decoupling capacitor. Using wafer bonding means that the decoupling capacitor can be added to the second wafer without having to take up space in the second wafer. In one embodiment, after bonding the first and second wafers, one or more vias are formed through the second wafer to establish an electrical connection between the decoupling capacitor and bond pads on a first surface of the second wafer. An electrical IC can then be flip chipped bonded to the first surface. As part of coupling the decoupling capacitor to the electrical IC, the decoupling capacitor is connected between the rails of a power source (e.g., VDD and VSS) that provides power to the electrical IC.

Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity.

The present disclosure describes a system 400 for transmitting power to a remote Power over Ethernet (PoE) subsystem by forwarding Powered Device (PD) input voltage where the subsystem includes a PD and a Power Sourcing Equipment (PSE) device. Included is a master PSE device 402, a first subsystem 410, and a second subsystem 428. The first subsystem 410 includes a first PD 418 that includes a first power switching device 426 and a first PSE device 424. The first power switching device 426 forwards the input power from the first PD 418 to the first PSE 424 without disturbing the PoE handshaking between the devices. The first power switching device 426 uses a switching device with level detection that detects the required input voltage. The second subsystem 428 receives the power from the first subsystem's 410 first PSE device 424. And the second subsystem 428 operates in a manner similar to the first subsystem 410.

A circuit carrier includes a first side, two layers arranged to define an intermediate space there between, with at least one of the two layers being electrically conductive and attached to the first side. The at least one of the two layers has a region deformed such as to exhibit an indentation and has a trace structure in the indentation. A first insulating material fills the intermediate space, and a second insulating material fills the indentation, A second side in opposition to the first side is shaped to have in the deformed region a cut-out for receiving a bare die such as to come into an electrical contact with the at least one of the two layers.

Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.