A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.

A display device and method for fabrication thereof are provided. The display device includes a first substrate, pixel electrodes on the first substrate, light emitting elements respectively on the pixel electrodes, and including first semiconductor layers, second semiconductor layers, active layers respectively between the first semiconductor layers and the second semiconductor layers, a first light emitting element including a first active layer of the active layers, a second light emitting element including a second active layer of the active layers that is different from the first active layer, a third light emitting element including a third active layer of the active layers that is different from the first and second active layers, and a fourth light emitting element including a fourth active layer of the active layers that is different from the first to third active layers, and a common electrode layer on the light emitting elements.

A semiconductor package includes: a first wiring structure including a first wiring layer, and a second wiring layer disposed on the first wiring layer, and connected to a first connecting structure placed disposed on the first wiring layer; a first semiconductor chip disposed on the first wiring structure and connected to the first wiring structure through a first connecting pad disposed on a first side of the first semiconductor chip; a second wiring structure disposed on the first semiconductor chip; and an insulating member disposed between the first and second wiring structures, wherein the first wiring structure further includes a first signal pattern that is electrically connected to the first connecting pad, and the first signal pattern redistributes the first connecting pad to the first connecting structure via the insulating member.

A semiconductor module includes at least two semiconductor elements connected in parallel; a control circuit board placed between the at least two semiconductor elements; a control terminal for external connection; a first wiring member that connects the control terminal and the control circuit board; and a second wiring member that connects a control electrode of one of the at least two semiconductor elements and the control circuit board, wherein the second wiring member is wire-bonded from the control electrode towards the control circuit board, and has a first end on the control electrode and a second end on the control circuit board, the first end having a cut end face facing upward normal to a surface of the control electrode and the second end having a cut end face facing sideways parallel to a surface of the control circuit board.

A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

A substrate debonding apparatus configured to separate a support substrate attached to a first surface of a device substrate by an adhesive layer, the substrate debonding apparatus including a substrate chuck configured to support a second surface of the device substrate, the second surface being opposite to the first surface of the device substrate; a light irradiator configured to irradiate light to an inside of the adhesive layer; and a mask between the substrate chuck and the light irradiator, the mask including an opening through which an upper portion of the support substrate is exposed, and a first cooling passage or a second cooling passage, the first cooling passage being configured to provide a path in which a coolant is flowable, the second cooling passage being configured to provide a path in which air is flowable and to provide part of the air to a central portion of the opening.

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

Provided is a power semiconductor module that can secure insulating properties. A semiconductor element is mounted on a resin-insulated base plate including a circuit pattern, a resin insulating layer, and a base plate. A case enclosing the resin-insulated base plate is bonded to the resin insulating layer with an adhesive. The resin insulating layer and the case are bonded together with a region enclosed by the resin insulating layer and a tapered portion of the case formed closer to the resin insulating layer being filled with the adhesive made of a material identical to that of the sealing resin. Air bubbles in the adhesive appear in the tapered portion opposite to the resin insulating layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.