This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion.

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding.

A process for bonding chips to a substrate by direct bonding includes providing a support with which the chips are in contact, the chips in contact with the support being separate from one another. This bonding process also includes forming a liquid film on one face of the substrate, bringing the chips into contact with the liquid film, where the action of bringing the chips into contact with the liquid film causes attraction of the chips toward the substrate, and evaporating the liquid film in order to bond the chips to the substrate by direct bonding.

There is provided a light-detecting device. A light-detecting device includes a first substrate including a first electrode, a semiconductor layer, a first insulating film, and a via, and a second substrate that faces the first substrate and is electrically connected to the semiconductor layer through the via. The semiconductor layer includes a compound semiconductor material. The first electrode includes a first portion and the second portion. The first portion of the first electrode is in contact with the semiconductor layer, and the second portion is in contact with both the first insulating film and the via.

Methods and apparatus for processing a first substrate and a second substrate are provided herein. For example, a method of processing a substrate using extended spectroscopic ellipsometry (ESE) includes directing a beam from an extended spectroscopic ellipsometer toward a first surface of a first substrate and a second surface of a second substrate, which is different than the first substrate, determining in-situ ESE data from each of the first surface and the second surface during processing of the first substrate and the second substrate, measuring a change of phase and amplitude in determined in-situ ESE data, and determining one or more parameters of the first surface of the first substrate and the second surface of the second substrate using simultaneously complex dielectric function, optical conductivity, and electronic correlations from the measured change of phase and amplitude in the in-situ ESE data.

Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

A method of manufacturing a bonded structure includes providing a first semiconductor structure including a first die, a first dielectric layer and a first conductive pad electrically connected to the first die and surrounded by the first dielectric layer; providing a second semiconductor structure including a second die, a second dielectric layer and a second conductive pad electrically connected to the second die and surrounded by the second dielectric layer; providing a carrying module including a holding unit configured to hold the second semiconductor structure and an anchoring unit movably attached to the holding unit, wherein the anchoring unit includes an end portion; disposing the carrying module and the second semiconductor structure over the first semiconductor structure; and displacing the anchoring unit towards the first semiconductor structure to make the end portion in contact with the first dielectric layer.

A method for bonding semiconductor devices is provided. The method may include several operations. A wafer and a chip are formed. The wafer and the chip are disposed in a low-pressure environment. A planar surface of the chip is moved toward a planar surface of the wafer. A void is formed between the planar surface of the chip and the planar surface of the wafer. The chip is bonded to the wafer. A bonded structure of the chip and the wafer is disposed under a standard atmosphere and a size of the void is reduced. A system for forming a semiconductor structure is also provided.