A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

An inductor built-in substrate includes a core substrate having openings and first through holes, a magnetic resin filled in the openings and having second through holes, first through-hole conductors formed in the first through holes respectively such that each of the first through-hole conductors includes a metal film, and second through-hole conductors formed in the second through holes respectively such that each of the second through-hole conductors includes a metal film and that the metal film in each of the first through-hole conductors has a thickness that is greater than a thickness of the metal film in each of the second through-hole conductors.

Various embodiments relate to an integrated circuit including a transistor device having input and output terminals, and an inductor-capacitor (LC) circuit coupled to one of the terminals of the transistor device. The LC circuit includes a capacitor having a top plate and a bottom plate, a inductor having a coil structure, and a connector configured to couple the inductor and an interior portion the top plate of the capacitor. The inductor at least partially overlaps the capacitor.

An integrated electronic circuit including: a dielectric body delimited by a front surface; A top conductive region of an integrated electronic circuit extend within a dielectric body having a front surface. A passivation structure including a bottom portion and a top portion laterally delimits an opening. The bottom portion extends on the front surface, and the top portion extends on the bottom portion. A field plate includes an internal portion and an external portion. The internal portion is located within the opening and extends on the top portion of the passivation structure. The external portion extends laterally with respect to the top portion of the passivation structure and contacts at a bottom one of: the dielectric body or the bottom portion of the passivation structure. The opening and the external portion are arranged on opposite sides of the top portion of the passivation structure.

Embodiments described herein may be related to apparatuses, processes, and techniques related to inductors located within a substrate. An inductor may be created in a glass core using a laser-assisted etching of glass interconnects techniques to create trenches or vias within the glass substrate, into which conductive material may be plated or filled to create the inductor. In embodiments, the inductors may be low equivalent series resistance (ESR) compact air-core inductors. Other embodiments may be described and/or claimed.

An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

The disclosure relates to integrated circuits and methods of manufacture. A method involves forming a first set of one or more circuit layers on a semiconductor substrate, placing at least one prefabricated layer portion onto the first set of circuit layers to form a component, and forming a second set of one or more circuit layers over the first set of circuit layers and the at least prefabricated layer portion. The prefabricated layer portion may be a magnetic layer portion placed to form a magnetic component such as a magnetic core of an inductor or transformer. The method may also comprise forming the prefabricated layer portion.

A method for fabricating an electrical or electronic device package includes providing a first plateable encapsulation layer; activating first selective areas on a main surface of the first plateable encapsulation layer; forming a first metallization layer by electrolytic or electroless plating on the first activated areas; and fabricating a passive electrical component on the basis of the first metallization layer.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.