A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

Various embodiments relate to an integrated circuit including a transistor device having input and output terminals, and an inductor-capacitor (LC) circuit coupled to one of the terminals of the transistor device. The LC circuit includes a capacitor having a top plate and a bottom plate, a inductor having a coil structure, and a connector configured to couple the inductor and an interior portion the top plate of the capacitor. The inductor at least partially overlaps the capacitor.

A resistance element includes a resistive film, in which the resistive film is adjacent to a protrusion formed on a surface of a semiconductor substrate, the protrusion including a step traversed by the resistive film.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

A resistor circuit, an artificial intelligence chip and a method for manufacturing the same are provided. The resistor circuit includes a stack structure. The stack structure includes resistive material layers and insulating layers stacked alternately. The resistor circuit includes at least two unit resistors electrically connected in series or parallel. The at least two unit resistors are respectively defined in the resistive material layers of different layers.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a passivation layer covering the first gate conductor, and a second gate conductor disposed on the passivation layer and on a second region of the second nitride semiconductor layer, wherein the first region is laterally spaced apart from the second region.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a nitride semiconductor layer disposed on the substrate, a first gate stack in contact with the nitride semiconductor layer, and a resistor laterally spaced apart from the first gate stack and electrically connected to first gate stack. The resistor comprises a first conductive terminal in contact with the nitride semiconductor layer, a second conductive terminal in contact with the nitride semiconductor layer; a first doped region of the nitride semiconductor layer between the first conductive terminal and the second conductive terminal; and a first conductive region of the nitride semiconductor layer in contact with the first conductive terminal and the second conductive terminal.

The disclosure relates to a semiconductor die, including a vertical power transistor device, a pull-down transistor device, and a capacitor. The pull-down transistor device is connected between a gate electrode of the vertical power transistor device and a ground terminal and connects the gate electrode to the ground terminal in a conducting state. The capacitor is connected between one of the load terminals of the vertical power transistor device and the control terminal of the pull-down transistor device and capacitively couples the one load terminal to the control terminal.

A semiconductor device that is of a face-down mounted chip-size package type, discharges electric charges stored in an electric storage device (battery), and has a power loss area ratio of at least 0.4 (W/mm.sup.2) obtained by dividing a power loss (W) in the semiconductor device at time of the discharge by an area (mm.sup.2) of the semiconductor device, the semiconductor device comprising: a field-effect transistor of a horizontal type and a resistor that are connected in series in stated order between an inflow terminal and an outflow terminal; and a control circuit that causes a discharge current to be constant without depending on an applied voltage between the inflow terminal and the outflow terminal. A difference between a maximum temperature of a field-effect transistor portion and a temperature of a resistor portion is within five degrees Celsius in a discharge period.

A method for fabricating an electrical or electronic device package includes providing a first plateable encapsulation layer; activating first selective areas on a main surface of the first plateable encapsulation layer; forming a first metallization layer by electrolytic or electroless plating on the first activated areas; and fabricating a passive electrical component on the basis of the first metallization layer.