According to one embodiment, a semiconductor device includes a substrate having a first surface and an insulator that surrounds a first region of the first surface. A gate electrode is on the first region and has a first resistivity. A first conductor is also on the first region. The first conductor comprises a same material as the gate electrode, but has a second resistivity that is different from the first resistivity. The resistivity may be different, for example, by either use of different dopants/impurities or different concentrations of dopants/impurities. Resistivity may also be different due to inclusion of a metal silicide on the conductors or not.

The present application provides a method for manufacturing an integrated metal resistance layer, comprising: step 1, selecting a formation position of a metal resistance layer, wherein the formation position of the metal resistance layer is located on the surface of an interlayer film inlaid with a copper connection; step 2, completing formation processes of the selected copper connection and the selected interlayer film; step 3, forming the metal resistance layer, comprising the following sub-steps: step 31, depositing a material layer of the metal resistance layer; and step 32, performing patterned etching on the material layer of the metal resistance layer to form the metal resistance layer in the selected region; and step 4, forming a next copper connection and a via at the bottom of the next copper connection, wherein the vias at the bottom of the next copper connection have two different heights.

Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits, and a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads. The cell array structure may include a resistor pattern positioned at the same level as the semiconductor layer, a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer, and vertical structures penetrating the stack.

A heating device is provided. The heating device includes a substrate, a thin-film transistor disposed on the substrate, a heater disposed on the substrate, and a bridging component. The thin-film transistor includes a gate, a semiconductor layer, a source, and a drain. The bridging component is electrically connected to the heater and either the source or the drain. A method for fabricating the heating device is also provided.

A semiconductor device includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, a third semiconductor layer, a gate electrode, a first layer, and an insulating layer. The first and second semiconductor layers have first and second conductivity types. The third semiconductor layer has the second conductivity type, and is provided on the first semiconductor layer and disposed side-by-side with the second semiconductor layer in a first direction. The gate electrode is provided on the first semiconductor layer and between the second and third semiconductor layers. The first layer has a lower impurity concentration than the second semiconductor layer, is provided on the first semiconductor layer and, at one end thereof, is in contact with the second semiconductor layer. The insulating layer is provided on the first layer and, at one end thereof, is in contact with the second semiconductor layer.

An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

A monolithic optoelectronic integrated circuit is provided, including: a substrate including photonic integrated device region and a peripheral circuit region; a first GaN-based multi-quantum well optoelectronic PN-junction device including a first P-type ohmic contact electrode and a first N-type ohmic contact electrode; and a first GaN-based field-effect transistor, where the first GaN-based field-effect transistor includes a first gate dielectric layer disposed on the surface of the substrate and having a first recess, a first gate filled within the first recess, and a first source and a first drain that are disposed the opposite sides of the first gate, where the first source is electrically connected to the first P-type ohmic contact electrode, the first drain is configured to be electrically connected to a first potential.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.