A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.

Various embodiments relate to an integrated circuit including a transistor device having input and output terminals, and an inductor-capacitor (LC) circuit coupled to one of the terminals of the transistor device. The LC circuit includes a capacitor having a top plate and a bottom plate, a inductor having a coil structure, and a connector configured to couple the inductor and an interior portion the top plate of the capacitor. The inductor at least partially overlaps the capacitor.

A semiconductor device and semiconductor package, the device including a lower semiconductor chip including a lower through-electrode; an interposer mounted on the lower semiconductor chip, the interposer including an interposer substrate; a plurality of interposer through-electrodes penetrating through at least a portion of the interposer substrate in a vertical direction and electrically connected to the lower through-electrode; and at least one capacitor in the interposer substrate and electrically connected to at least one interposer through-electrode of the plurality of interposer through-electrodes; and an upper semiconductor chip mounted on the interposer and electrically connected to the interposer through-electrode.

The present disclosure generally relates to semiconductor structures for capacitive isolation, and structures incorporating the same. More particularly, the present disclosure relates to capacitive isolation structures for high voltage applications. The present disclosure also relates to methods of forming structures for capacitive isolation and the structures incorporating the same. The disclosed semiconductor structures may enable a smaller device footprint and reduced dimensions of components on an IC chip, whilst ensuring galvanic isolation between circuits.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

A method for fabricating a capacitor includes forming a first electrode, forming a dielectric layer stack on the first electrode, the dielectric layer stack including an initial hafnium oxide layer and a seed layer having a doping layer embedded therein, forming a thermal source layer on the dielectric layer stack to crystallize the initial hafnium oxide into tetragonal hafnium oxide, and forming a second electrode on the thermal source layer.

Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.

Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.