The present invention relates to a color tunable and/or color temperature tunable LED filament (20, 22, 24), said LED filament comprising an elongated carrier (220), said elongated carrier comprising a first major surface (222) and a second major surface (224) arranged opposite to said first major surface, a plurality of LEDs (210) arranged in at least one linear array on said first surface of said elongated carrier, wherein the plurality of LEDs includes LEDs of different colors and/or different color temperatures, a first elongated transparent or substantially transparent layer (230) covering the plurality of LEDs on the first major surface and also at least partly covering said first major surface, and a first elongated light scattering layer (240), arranged to at least partially cover said first transparent or substantially transparent layer.

A light emitting device including a substrate, a first semiconductor layer disposed on the substrate, a mesa including a second semiconductor layer and an active layer disposed on the first semiconductor layer, a first contact electrode contacting the first semiconductor layer, a second contact electrode contacting the second semiconductor layer, a passivation layer covering the first contact electrode, the mesa, and the second contact electrode, and including a first opening disposed on the first contact electrode and a second opening disposed on the second contact electrode, and first and second bump electrodes electrically connected to the first and second contact electrodes through the first and second openings, respectively, in which the first and second bump electrodes are disposed on the mesa, the passivation layer is disposed between the first bump electrode and the second contact electrode, and the first contact electrode includes an alloy layer.

A light emitting device including a substrate, a first semiconductor layer disposed on the substrate, a mesa including a second semiconductor layer and an active layer disposed on the first semiconductor layer, a first contact electrode contacting the first semiconductor layer, a second contact electrode contacting the second semiconductor layer, a passivation layer covering the first contact electrode, the mesa, and the second contact electrode, and including a first opening disposed on the first contact electrode and a second opening disposed on the second contact electrode, and first and second bump electrodes electrically connected to the first and second contact electrodes through the first and second openings, respectively, in which the first and second bump electrodes are disposed on the mesa, the passivation layer is disposed between the first bump electrode and the second contact electrode, and the first contact electrode includes an alloy layer.

A display device includes a first electrode and a second electrode, spaced apart from each other, and a light emitting element disposed between the first electrode and the second electrode. The light emitting element includes a core area and a doping area surrounding the core area.

A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface of a crystal layer of the group 13 nitride includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, observed by cathode luminescence. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride. The crystal of the nitride of the group 13 element contains oxygen atoms in a content of 1×10.sup.18 atom/cm.sup.3 or less, silicon atoms, manganese atoms, carbon atoms, magnesium atoms and calcium atoms in contents of 1×10.sup.17 atom/cm.sup.3 or less, chromium atoms in a content of 1×10.sup.16 atom/cm.sup.3 or less and chlorine atoms in a content of 1×10.sup.15 atom/cm.sup.3 or less.

A light-emitting element includes a first semiconductor layer doped with an n-type dopant, a second semiconductor layer doped with a p-type dopant, a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, and an insulating film that surrounds the first semiconductor layer, the second semiconductor layer, and the light emitting layer. A doping concentration of the first semiconductor layer is in a predetermined range. A display device includes the light-emitting element.

An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.

A method includes forming a first n-type nitride semiconductor layer; forming a first light-emitting layer on the first n-type nitride semiconductor layer; forming a first nitride semiconductor layer on the first light-emitting layer by introducing a gas comprising gallium and having a first flow rate; forming a first p-type nitride semiconductor layer on the first nitride semiconductor layer; forming an n-type intermediate layer on the first p-type nitride semiconductor layer; forming a second n-type nitride semiconductor layer on the n-type intermediate layer; forming a second light-emitting layer on the second n-type nitride semiconductor layer; forming a second nitride semiconductor layer on the second light-emitting layer by introducing a gas comprising gallium and having a second flow rate; and forming a second p-type nitride semiconductor layer on the second nitride semiconductor layer. The first flow rate is less than the second flow rate.

The invention relates to a method for producing a light-emitting diode comprising a semiconductor stack formed of a first layer 11, of an active layer 13, and of an extraction layer 6. It comprises a step of determining a distance h.sub.1s between emitting dipoles μ.sub.1 that are located in the active layer 13 and the extraction layer 6, such that the emitting dipoles μ.sub.1 of vertical orientation have in particular a lifetime longer than that of the emitting dipoles of horizontal orientation.

The present disclosure falls into the field of optoelectronics, particularly, includes the design, epitaxial growth, fabrication, and characterization of Laser Diodes (LDs) operating in the ultraviolet (UV) to infrared (IR) spectral regime on patterned substrates (PSs) made with (formed on) low cost, large size Si, or GaN on sapphire, GaN, and other wafers. We disclose three types of PSs, which can be universal substrates, allowing any materials (III-Vs, II-VIs, etc.) grown on top of it with low defect and/or dislocation density.