A micro LED touch display pane of reduced thickness includes a substrate, a display driving layer, micro LEDs on the display driving layer, and common electrodes connecting to the micro LEDs. The micro LEDs are spaced apart from each other and coupled to the display driving layer. The common electrodes cover the micro LEDs. The touch display panel further includes first and second electrodes. The common electrodes and the first electrodes are defined in one layer, insulated from the second electrodes. The first electrodes and the second electrodes cooperatively form mutual-capacitance touch sensing structures.

The method for assembling a carrier comprises a step A), in which a plurality of pigments (100), each with an electronic component (1), is provided. Further, each pigment comprises a meltable solder material (2) directly adjoining a mounting side (10) of the component. At least 63% by volume of each pigment is formed by the solder material. The mounting side of each component has a higher wettability with the molten solder material than a top side (12) and a side surface (11) of the component. In a step B), a carrier (200) with pigment landing areas (201) is provided, the pigment landing areas having higher wettability with the molten solder material of the pigments than the regions laterally adjacent to the pigment landing areas and than the side surfaces and the top sides of the components. In a step C), the pigments are applied to the carrier. In a step D), the pigments are heated so that the solder material melts.

The method for assembling a carrier comprises a step A), in which a plurality of pigments (100), each with an electronic component (1), is provided. Further, each pigment comprises a meltable solder material (2) directly adjoining a mounting side (10) of the component. At least 63% by volume of each pigment is formed by the solder material. The mounting side of each component has a higher wettability with the molten solder material than a top side (12) and a side surface (11) of the component. In a step B), a carrier (200) with pigment landing areas (201) is provided, the pigment landing areas having higher wettability with the molten solder material of the pigments than the regions laterally adjacent to the pigment landing areas and than the side surfaces and the top sides of the components. In a step C), the pigments are applied to the carrier. In a step D), the pigments are heated so that the solder material melts.

In a flip chip type light-emitting diode, a light-emitting diode structure possesses one unique layer with properties of both thermal conduction and electrical isolation disposed on its second contact metal layer. A first dielectric layer covers the light-emitting diode structure. A first-level metal interconnect is divided into three blocks, which are disposed on the first dielectric layer and are respectively connected to a first contact metal layer, the second contact metal layer, and the insulated heat-transfer layer. A first bonding pad structure, a second bonding pad structure, and a heat-dissipating pad structure, forming a second-level interconnect metal layer, are disposed on a second dielectric layer and respectively connected to the blocks of the first-level metal interconnect. The first bonding pad structure, the second bonding pad structure, and the heat-dissipating pad structure are respectively disposed on a first electrode, a second electrode, and a heat-dissipating electrode of a circuit board.

In a flip chip type light-emitting diode, a light-emitting diode structure possesses one unique layer with properties of both thermal conduction and electrical isolation disposed on its second contact metal layer. A first dielectric layer covers the light-emitting diode structure. A first-level metal interconnect is divided into three blocks, which are disposed on the first dielectric layer and are respectively connected to a first contact metal layer, the second contact metal layer, and the insulated heat-transfer layer. A first bonding pad structure, a second bonding pad structure, and a heat-dissipating pad structure, forming a second-level interconnect metal layer, are disposed on a second dielectric layer and respectively connected to the blocks of the first-level metal interconnect. The first bonding pad structure, the second bonding pad structure, and the heat-dissipating pad structure are respectively disposed on a first electrode, a second electrode, and a heat-dissipating electrode of a circuit board.

The present invention relates to a load arrangement for use in an electrical power arrangement and for arrangement at a first external electrically conductive element (5). The load arrangement comprises a load (2), a first electrode (3) electrically connected to the load (2), a dielectric layer (4) and a carrier carrying the load (2), the first electrode (3) and the dielectric layer (4). The load (2), the first electrode (3) and the dielectric layer (4) form a structure, which is configured for being arranged at the first external electrically conductive element (5). The first electrode (3) and the dielectric layer (4) are arranged to form, in combination with a first external electrically conductive element (5) representing an outer surface of a marine structure, a capacitor (6) for capacitive transmission of electrical power between the first electrode (3) and the first external element (5). The carrier is configured for being arranged at the first external electrically conductive element (5). The load (2) is connected to a second electrode (7) electrically insulated from the first electrode (3) or is arranged for being electrically connected to a second external electrically conductive element (10, 11) electrically insulated from the first electrode (3).

The present invention relates to a load arrangement for use in an electrical power arrangement and for arrangement at a first external electrically conductive element (5). The load arrangement comprises a load (2), a first electrode (3) electrically connected to the load (2), a dielectric layer (4) and a carrier carrying the load (2), the first electrode (3) and the dielectric layer (4). The load (2), the first electrode (3) and the dielectric layer (4) form a structure, which is configured for being arranged at the first external electrically conductive element (5). The first electrode (3) and the dielectric layer (4) are arranged to form, in combination with a first external electrically conductive element (5) representing an outer surface of a marine structure, a capacitor (6) for capacitive transmission of electrical power between the first electrode (3) and the first external element (5). The carrier is configured for being arranged at the first external electrically conductive element (5). The load (2) is connected to a second electrode (7) electrically insulated from the first electrode (3) or is arranged for being electrically connected to a second external electrically conductive element (10, 11) electrically insulated from the first electrode (3).

An optoelectronic semiconductor component includes a light-emitting semiconductor body having a radiation side, a current expansion layer arranged on the radiation side of the semiconductor body and at least partially covers this side, wherein the current expansion layer includes an electrically-conductive material transparent to the light radiated by the semiconductor body, and particles of a further material, and an electrical contact arranged on a side of the current expansion layer facing away from the semiconductor body.

A method of manufacturing a patterned substrate includes: providing an exposure mask, the exposure mask comprising: a plurality of inner light-shielding portions arranged in a lattice, a light-transmissive portion integrally connecting regions surrounding the plurality of inner light-shielding portions, and an outer light-shielding portion surrounding the light-transmissive portion; performing a plurality of exposures of a photoresist layer disposed on a substrate in a step-and-repeat-manner using the exposure mask, so as to form a plurality of inner projected parts corresponding to the inner light-shielding portions, the inner projected parts being aligned in a lattice as a whole; developing the photoresist layer on which the plurality of exposures have been performed; and etching the substrate using the developed photoresist layer as a mask; wherein, in the step of performing the plurality of exposures, a region corresponding to the light-transmissive portion formed by a predetermined one of the exposures and a region corresponding to the light-transmissive portion formed by another one of the exposures do not overlap each other on shortest straight lines connecting outermost inner projected parts formed by the predetermined exposure and respective inner projected parts formed by the another exposure that are located closest to the outermost inner projected parts of the predetermined exposure, while portions of the region corresponding to the light-transmissive portion formed by the predetermined exposure and portions of the region corresponding to the light-transmissive portion formed by the another exposure overlap each other in places other than the shortest straight lines.

A method of manufacturing a patterned substrate includes: providing an exposure mask, the exposure mask comprising: a plurality of inner light-shielding portions arranged in a lattice, a light-transmissive portion integrally connecting regions surrounding the plurality of inner light-shielding portions, and an outer light-shielding portion surrounding the light-transmissive portion; performing a plurality of exposures of a photoresist layer disposed on a substrate in a step-and-repeat-manner using the exposure mask, so as to form a plurality of inner projected parts corresponding to the inner light-shielding portions, the inner projected parts being aligned in a lattice as a whole; developing the photoresist layer on which the plurality of exposures have been performed; and etching the substrate using the developed photoresist layer as a mask; wherein, in the step of performing the plurality of exposures, a region corresponding to the light-transmissive portion formed by a predetermined one of the exposures and a region corresponding to the light-transmissive portion formed by another one of the exposures do not overlap each other on shortest straight lines connecting outermost inner projected parts formed by the predetermined exposure and respective inner projected parts formed by the another exposure that are located closest to the outermost inner projected parts of the predetermined exposure, while portions of the region corresponding to the light-transmissive portion formed by the predetermined exposure and portions of the region corresponding to the light-transmissive portion formed by the another exposure overlap each other in places other than the shortest straight lines.