The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (TIM) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core, where a top surface of the TGV is not coplanar with a top surface of the core. In an embodiment, the electronic package further comprises a ridge on the top surface of the TGV, where the ridge is symmetric about a centerline of the TGV.

Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

A semiconductor package is described which meets a plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package includes a semiconductor die embedded in or covered by a molded plastic body, the molded plastic body satisfying only a subset of the plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package further includes a plurality of terminals protruding from the molded plastic body and electrically connected to the semiconductor die, and a coating applied to at least part of the molded plastic body and/or part of the plurality of terminals. The coating satisfies each predetermined electrical, mechanical, chemical and/or environmental requirement not satisfied by the molded plastic body.

A carbon-coated thermal conductive material includes a coating layer comprising amorphous carbon on a surface of a thermal conductive material, wherein the thermal conductive material comprises a metal oxide, a metal nitride, a metal material, or a carbon-based material having a thermal conductivity of 10 W/mK or greater, the amorphous carbon is derived from carbon contained in an oxazine resin, a ratio of a peak intensity of a G band to a peak intensity of a D band is 1.0 or greater when the amorphous carbon is measured by Raman spectroscopy, an average film thickness of the coating layer is 500 nm or less, and a coefficient of variation (CV value) of a film thickness of the coating layer is 15% or less.

Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (TIM) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

A light emitting device according to an embodiment includes a substrate; first to Mth light emitting cells (where M is a positive integer of two or more) which are arranged on the substrate so as to be spaced apart from each other; and first to (M1)th interconnection wires which electrically connect the first to Mth light emitting cells in series, wherein an mth light emitting cell (where 1mM) includes a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, which are sequentially arranged on the substrate, and wherein an nth interconnection wire (where 1nM1) interconnects the first conductive type semiconductor of the nth light emitting cell with the second conductive type semiconductor of the (n+1)th light emitting cell, and has a plurality of first branch wires which are spaced apart from each other.