Disclosed is a fan-out antenna packaging method. A front surface of a semiconductor chip is jointed to a top surface of a separating layer; side surfaces and a bottom surface of the semiconductor chip are merged into a packaging layer; the packaging layer is separated from the separating layer to expose the front surface of the semiconductor chip; a rewiring layer is electrically connected to the semiconductor chip; a first antenna structure and a second antenna are stacked on a top surface of the rewiring layer, the antenna structures is electrically connected to the rewiring layer; a through hole runs through the packaging layer and exposes a metal wiring layer in the rewiring layer; and a metal bump electrically connected to the metal wiring layer is formed by using the through hole.

Disclosed is a fan-out antenna packaging method. A front surface of a semiconductor chip is jointed to a top surface of a separating layer; side surfaces and a bottom surface of the semiconductor chip are merged into a packaging layer; the packaging layer is separated from the separating layer to expose the front surface of the semiconductor chip; a rewiring layer is electrically connected to the semiconductor chip; a first antenna structure and a second antenna are stacked on a top surface of the rewiring layer, the antenna structures is electrically connected to the rewiring layer; a through hole runs through the packaging layer and exposes a metal wiring layer in the rewiring layer; and a metal bump electrically connected to the metal wiring layer is formed by using the through hole.

A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant. The top metal layers, the bottom metal layers, and the intermetallic layers are in contact with the first encapsulant.

A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant. The top metal layers, the bottom metal layers, and the intermetallic layers are in contact with the first encapsulant.

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.