Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

The semiconductor device includes a semiconductor substrate having a main surface and a back surface, an device isolation film, formed over the main surface of the semiconductor substrate and having a first surface making contact with the main surface and a second surface opposed to the first surface, a plate electrode disposed over the device isolation film in contact with the second surface of the device isolation film, and a pad electrode disposed adjacent to the first surface of the device isolation film and making contact with the plate electrode.

The semiconductor substrate has a first opening that passes therethrough from the back surface to the main surface and exposes the device isolation film. The device isolation film has a second opening located in the first opening and exposes a part of the plate electrode. The pad electrode is formed in the second opening and extends over the first surface of the device isolation film.

The semiconductor device includes a semiconductor substrate having a main surface and a back surface, an device isolation film, formed over the main surface of the semiconductor substrate and having a first surface making contact with the main surface and a second surface opposed to the first surface, a plate electrode disposed over the device isolation film in contact with the second surface of the device isolation film, and a pad electrode disposed adjacent to the first surface of the device isolation film and making contact with the plate electrode.

The semiconductor substrate has a first opening that passes therethrough from the back surface to the main surface and exposes the device isolation film. The device isolation film has a second opening located in the first opening and exposes a part of the plate electrode. The pad electrode is formed in the second opening and extends over the first surface of the device isolation film.

Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.