A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.

A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.

One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

A method for evaluating pickup property of a dicing/die-bonding integrated film including a base layer, an adhesive, and a bonding adhesive layer in order, the method including preparing a laminate including the dicing/die-bonding integrated film and a wafer having a thickness of 10 to 100 μm laminated on the bonding adhesive layer, singulating the wafer into a plurality of chips having an area of 9 mm.sup.2 or less, pushing a center portion of the chip from a side of the base layer, and measuring a peeling strength when an edge of the chip is peeled off from the adhesive layer.

A method for evaluating pickup property of a dicing/die-bonding integrated film including a base layer, an adhesive, and a bonding adhesive layer in order, the method including preparing a laminate including the dicing/die-bonding integrated film and a wafer having a thickness of 10 to 100 μm laminated on the bonding adhesive layer, singulating the wafer into a plurality of chips having an area of 9 mm.sup.2 or less, pushing a center portion of the chip from a side of the base layer, and measuring a peeling strength when an edge of the chip is peeled off from the adhesive layer.