A fan motor stopping apparatus includes a conversion circuit that converts alternating-current voltage supplied from an alternating-current power supply into direct-current voltage, a smoothing capacitor that is connected to a fan motor included in an air conditioner and smooths the direct-current voltage from the conversion circuit, a voltage detection circuit that detects a voltage across the smoothing capacitor, and a fan motor shutdown circuit that suspends the fan motor in operation when the voltage detection circuit detects a voltage less than or equal to a threshold that is preset for suspending the operation of the fan motor.

A battery secondary protection circuit and a mode switching method thereof are disclosed. The battery secondary protection circuit is coupled in series with a battery primary protection circuit and has a power pin and a sensing pin. The switching method includes steps of: (S1) determining whether a voltage difference between the power pin and the sensing pin is greater than a default value; and (S2) selectively switching the battery secondary protection circuit to a first mode or a second mode according to a determination result of the step (S1). The battery secondary protection circuit delays a first delay time and a second delay time in the first mode and the second mode respectively and then performs a circuit protection operation. The first delay time is longer than the second delay time.

An eFuse for use in high voltage applications is disclosed. In one embodiment, an apparatus includes a solid-state switch having source and drain terminals connected to switch a load current from a high voltage source through a high voltage load. The apparatus also includes a sense circuit that senses a voltage between the switch source and drain terminals and turns off the switch when the voltage exceeds a selected voltage level.

A matrix converter includes one or more current sensors structured to sense current flowing through the matrix converter, a matrix of switches including a number of solid state transistors, and a control circuit structured to detect faults in power flowing through the matrix converter based on the sensed current, to control the matrix of switches to drive an external device, and to control the matrix of switches to switch to prevent power from flowing internal to the matrix converter, or external to the external device in response to detecting a fault in power flowing through the matrix converter.

A bi-directional direct current (DC) solid state power controller (SSPC) architecture and control method. The SSPC protects a DC distribution system by isolating both the positive and negative buses independently in case of short circuit or ground fault. The SSPC architecture includes two self-heal interleaved capacitors and includes a fast, soft-charging control technique that provides line-isolated charging of the DC bulk capacitor to avoid inrush current when powering up the DC distribution system. The soft-charging function alternately charges one of the two interleaved capacitors, while the other capacitor discharges to the DC bulk capacitor. Repetitive switching results in a charging and discharging process that increases the voltage of the DC bulk capacitor prior to powering up the DC distribution system, while keeping the DC power source isolated from the load.

Methods, apparatus, systems and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over current protection. An example apparatus includes an output terminal; a voltage detection device coupled to a voltage detection input terminal and the output terminal and including a voltage detection output coupled to a logic gate first input terminal; a pulse extender coupled between a logic gate output and a selecting node; a multiplexer coupled to the selecting node and configured to be coupled to a first protection circuit, a second protection circuit, and a driver; and a switch coupled between an input terminal and the output terminal and including a switch gate terminal coupled to the driver.

Methods, apparatus, systems and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over current protection. An example apparatus includes an output terminal; a voltage detection device coupled to a voltage detection input terminal and the output terminal and including a voltage detection output coupled to a logic gate first input terminal; a pulse extender coupled between a logic gate output and a selecting node; a multiplexer coupled to the selecting node and configured to be coupled to a first protection circuit, a second protection circuit, and a driver; and a switch coupled between an input terminal and the output terminal and including a switch gate terminal coupled to the driver.

Systems and methods for fault detection and protection in electric power systems that evaluates electromagnetic transients caused by faults. A fault can be detected using sampled data from a first monitored point in the power system. Detection of fault transients and associated characteristics, including transient direction, can also be extracted through evaluation of sample data from other monitored points in the power system. A monitoring device can evaluate whether to trip a switching device in response to the detection of the fault and based on confirmation of an indication of detection of fault transients at the other monitored points of the power system. The determination of whether to trip or activate the switching device can also be based on other factors, including the timing of receipt of an indication of the detection of the fault transients and/or an evaluation of the characteristics of the detected transients.

A device includes a protected terminal, a reference terminal, and a rate-triggered circuit coupled to the protected terminal and to the reference terminal. The rate-triggered circuit is configured to provide an output voltage responsive to a ramp rate of a voltage at the protected terminal being greater than a rate threshold. The device also includes a transistor configured to shunt current from the protected terminal to the reference terminal responsive to the rate-triggered circuit output voltage, and a level-sensing circuit configured to turn off the transistor responsive to the voltage at the protected terminal being greater than a level-sense threshold.

Embodiments of the present disclosure provide an over-voltage protection method, an over-voltage protection device and a display device. When the voltage value of the output signal is greater than the first preset voltage threshold, it is determined whether the voltage value of the output signal meets the preset over-voltage protection condition. If the voltage value of the output signal is detected to meet the preset over-voltage protection condition, the first control signal is output to stop output of the output signal or lower the voltage value of the output signal.