A power conversion device provided between a DC power supply and an AC electric path, including: a breaking device provided to at least one line of an output electric path in the power conversion device; a first voltage sensor provided on a primary side of the breaking device; a second voltage sensor provided on a secondary side of the breaking device; and a determination unit which calculates a primary-side voltage and a secondary-side voltage, and a primary-side phase and a secondary-side phase and determines that the breaking device is opened, by occurrence of an event in which an absolute value of a voltage difference between the primary-side voltage and the secondary-side voltage is greater than a voltage difference threshold value and an absolute value of a phase difference between the primary-side phase and the secondary-side phase is greater than a phase difference threshold value.

A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

A potential difference early-warning circuit, comprising: a sensing resistor (R2), (PCB GND); a first MOS (M1), a drain of the first MOS being connected to the sensing resistor (R2), and a source of the first MOS (M1) being connected to a safety ground (GND); an operational amplifier (U1A), a positive input end of the operational amplifier being connected to one end of the sensing resistor (R2), and a negative input end of the operational amplifier (U1A) being connected to the other end of the sensing resistor (R2); a second MOS (M2), a gate of the second MOS (M2) being connected to an output end of the operational amplifier (U1A), and a source of the second MOS (M2) being connected to the signal ground; and a controller, a first input end of the controller being connected to the drain of the second MOS (M2), and an output end of the controller being connected to the gate of the second MOS (M2).

A potential difference early-warning circuit, comprising: a sensing resistor (R2), (PCB GND); a first MOS (M1), a drain of the first MOS being connected to the sensing resistor (R2), and a source of the first MOS (M1) being connected to a safety ground (GND); an operational amplifier (U1A), a positive input end of the operational amplifier being connected to one end of the sensing resistor (R2), and a negative input end of the operational amplifier (U1A) being connected to the other end of the sensing resistor (R2); a second MOS (M2), a gate of the second MOS (M2) being connected to an output end of the operational amplifier (U1A), and a source of the second MOS (M2) being connected to the signal ground; and a controller, a first input end of the controller being connected to the drain of the second MOS (M2), and an output end of the controller being connected to the gate of the second MOS (M2).

An arc fault detection system includes a high frequency detector module structured to detect first spectral content of power having a frequency in a first frequency range, a number of arc fault circuit interrupters each having separable contacts, a low frequency detector module structured to detect second spectral content of power having a frequency in a second frequency range, a control unit structured to control the separable contacts to trip open, and an arc fault detection unit structured to detect an arc fault based on the detected first and second spectral content of the power and to cause the control unit to control the separable contacts to trip open in response to detecting the arc fault. A communication bus provides communication between the high frequency detector and the arc fault circuit interrupters and the first frequency range includes frequencies that are higher than frequencies in the second frequency range.

An arc fault detection system includes a high frequency detector module structured to detect first spectral content of power having a frequency in a first frequency range, a number of arc fault circuit interrupters each having separable contacts, a low frequency detector module structured to detect second spectral content of power having a frequency in a second frequency range, a control unit structured to control the separable contacts to trip open, and an arc fault detection unit structured to detect an arc fault based on the detected first and second spectral content of the power and to cause the control unit to control the separable contacts to trip open in response to detecting the arc fault. A communication bus provides communication between the high frequency detector and the arc fault circuit interrupters and the first frequency range includes frequencies that are higher than frequencies in the second frequency range.

A power conversion device provided between a DC power supply and an AC electric path, including: a breaking device provided to at least one line of an output electric path in the power conversion device; a first voltage sensor provided on a primary side of the breaking device; a second voltage sensor provided on a secondary side of the breaking device; and a determination unit which calculates a primary-side voltage and a secondary-side voltage, and a primary-side phase and a secondary-side phase and determines that the breaking device is opened, by occurrence of an event in which an absolute value of a voltage difference between the primary-side voltage and the secondary-side voltage is greater than a voltage difference threshold value and an absolute value of a phase difference between the primary-side phase and the secondary-side phase is greater than a phase difference threshold value

In described examples, a switch has: a first current handling terminal coupled to a supply source terminal; and a second current handling terminal coupled to an output terminal. A comparator has: a first input coupled to the second current handling terminal; and a second input. A voltage reference source has: a first terminal coupled to the first current handling terminal; and a second terminal coupled to the second input of the comparator. A slew rate detector has an input coupled to the second current handling terminal. A switch controller has: a first input coupled to the comparator output; and a second input coupled to an output of the slew rate detector. The switch controller is coupled to output a signal to cause the switch to open when the comparator detects an over-current condition through the switch while the slew rate detector detects a negative slew rate.

A circuit interrupter including a first electrical conductor, a second electrical conductor, separable contacts, an operating mechanism configured to open and close said separable contacts, a trip circuit configured to trip open said separable contacts, a ground fault detection circuit configured to sense a difference between a current through the first electrical conductor and a current through the second electrical conductor and to output an output signal based on said sensed difference, a power supply, a confirmation circuit structured to input a confirmation signal to the power supply, and a processor configured to receive said direct current power and said output signal. The processor is configured to determine whether a characteristic of said confirmation signal is present in said output signal and to control the trip circuit based on said determination.