Patent classifications
H02H9/005
POWER MANAGEMENT SYSTEM FOR MAINTAINING BUS VOLTAGE
Examples described herein relate to a power management system. The power management system may include an input power filter coupled between a common power bus having a first voltage level and a load. The input power filter may include a variable impedance circuit coupled to an input capacitor. Further, the power management system may include a bus voltage controller coupled to the input power filter to detect a transient event causing a surge in a load current drawn by the load and to alter an impedance of the variable impedance circuit to limit an input current flowing via the variable impedance circuit, thereby maintaining voltage on the common power bus within a predefined range from the first voltage level.
Method and systems for detection and protection from electromagnetic pulse events using hardware implemented artificial intelligence
A system and method for detecting and isolating a high-altitude electromagnetic pulse (“HEMP”) along electrical lines electrically connected to a monitored infrastructure so as to protect the monitored infrastructure, the method including a phase unit receiving sensor signals from a plurality of sensors electrically connected to each of the electrical lines, respectively, upstream of and associated with the monitored infrastructure. The method includes determining if the received sensors signals associated with the respective electrical line is indicative of an E1 component of an EMP and, if so, actuating an isolation subsystem in less than 300 nanoseconds to electrically isolate the respective electrical line against propagation against the monitored infrastructure. Determining in real time if received sensor signals is indicative of the E1 component includes a hardware implemented neural network (NN) having algorithms for machine learning (ML) and artificial intelligence (AI) operable to provide instantaneous detection and classification.
Current cut-off device for high-voltage direct current with capacitive buffer circuit, and control method
A high-voltage direct current cut-off device, includes: a primary mechanical switch and a secondary mechanical switch placed successively between a primary point and a secondary point but either side of an intermediate point, a primary surge arrester arranged parallel with the primary switch, a secondary surge arrester arranged electrically parallel with the secondary switch. The secondary surge arrester is arranged electrically between the intermediate point and the secondary point, and in that the device comprises a capacitive buffer circuit electrically in parallel with the assembly formed by the primary switch and the secondary switch, and electrically in parallel with the assembly formed by the primary surge arrester and the secondary surge arrester, wherein the capacitive buffer circuit comprises an activation switch and a buffer capacitance.
DISTRIBUTED ELECTRO-STATIC DISCHARGE PROTECTION
The present invention provides an integrated circuit layout including a first bank and a second bank. The first bank includes a plurality of I/O circuits and at least one first ESD clamp device. The second bank includes at least one second ESD clamp device, wherein the at least one second ESD clamp device is different in type from the at least one first ESD clamp device.
HIGH FREQUENCY DATA TRANSCEIVER AND SURGE PROTECTION RETROFIT FOR A SMART METER
A high frequency data recorder (“HFDR”) can include a first set of contacts, on a first side of the HFDR, that are pluggable into a first meter receptacle of a meter box, wherein the first meter receptacle provides a connection to a power supply and a connection to a load. The HFDR also includes a second set of contacts, on a second side of the HFDR, that form a second meter receptacle. The second meter receptacle provides another connection to the power supply and another connection to the load. The HFDR can further include a processor that accesses a non-transitory machine readable memory that stores instruction that when executed cause the processor to passively measures current downstream from the meter box. The HFDR still further includes a wireless transceiver that wirelessly transmits data characterizing the measured current.
WIRELESS POWER TRANSMITTERS WITH FRONT END VEHICULAR INPUT POWER PROTECTION
A power transmitter for wireless power transfer at extended distances is configured for vehicular utilization. The power transmitter includes vehicular power input regulator configured for receiving input power and filtering the input power to a filtered input power, the vehicular power input regulator including an input protection circuit and a DC/DC voltage converter. The power transmitter further includes a control and communications circuit and an inverter circuit. The power transmitter further includes a coil for transmitting the power signal to a power receiver, the coil formed of wound Litz wire and including at least one layer, each of the at least one layer having N turns, the coil defining, at least a top face and a shielding comprising a ferrite core and defining a cavity, the cavity configured such that the ferrite core substantially surrounds all but the top face of the coil.
Overvoltage protector with array of resistors
an overvoltage protector for protecting a device to be protected, having a first terminal and a second terminal. A number of strings are connected in parallel to one another between the first terminal and the second terminal, each string having a resistor, and at least one of the strings comprising a switching element that is connected in series to the resistor of the string. A circuit having an overvoltage protector, a use of an overvoltage protector, and a method for operating an overvoltage protector is also provided.
Protection circuit for terminal camera
A protection circuit and a printed circuit board (PCB) for a terminal camera includes, in a configuration for coupling with a voice control motor (VCM), a drive circuit, a first circuit, a second circuit, a first protection system, a second protection system, and a third protection system. The first circuit and the second circuit are choke inductors or choke circuits including choke inductors, and are configured to couple to two ends of the VCM. The first protection system, the second protection system, and the third protection system are coupled to other key positions of the circuits. The devices are arranged on a top layer of the PCB, and a plurality of layers of the PCB are configured to route a signal based on design requirements.
BATTERY SURGE REDUCTION USING A TRANSIENT AUXILIARY CONVERTER
A transient auxiliary converter includes: a transient auxiliary converter terminal; an inductor having a first side and a second side, the first side of the inductor coupled to the transient auxiliary converter terminal; a capacitor having a first electrode and a second electrode, the second electrode of the capacitor being coupled to ground; a first switch between the second side of the inductor and the first electrode of the capacitor; and a second switch between the second side of the inductor and ground. The first and second switches are operated in accordance with a charge mode and a transient response mode for the transient auxiliary converter. The charge mode builds up charge on the capacitor from charge at the transient auxiliary converter terminal. The transient response mode releases charge on the capacitor to the transient auxiliary converter terminal.
ESD PROTECTION CIRCUIT AND SEMICONDUCTOR DEVICE
The ESD protection circuit includes an off transistor including: a P-type semiconductor substrate; an N-type well region formed in an upper portion of the semiconductor substrate; an N-type drain region formed in an upper portion of the well region and having a higher impurity concentration than the well region; an N-type source region formed apart from the drain region in the upper portion of the well region and having a higher impurity concentration than the well region; a gate insulating film formed between the drain region and the source region; a gate electrode formed on a surface of the gate insulating film; and a P-type high-concentration region formed in the upper portion of the well region to be in contact with at least the drain region near a corner portion of a channel region and having a higher impurity concentration than the well region.