The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

Distributed maximum power point tracking systems, structures, and processes are provided for power generation structures, such as for but not limited to a solar panel arrays. In an exemplary solar panel string structure, distributed maximum power point tracking (DMPPT) modules are provided, such as integrated into or retrofitted for each solar panel. The DMPPT modules provide panel level control for startup, operation, monitoring, and shutdown, and further provide flexible design and operation for strings of multiple panels. The strings are typically linked in parallel to a combiner box, and then toward and enhanced inverter module, which is typically connected to a power grid. Enhanced inverters are controllable either locally or remotely, wherein system status is readily determined, and operation of one or more sections of the system are readily controlled. The system provides increased operation time, and increased power production and efficiency, over a wide range of operating conditions.

Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

An electrostatic discharge (ESD), protection device is provided. In accordance with the present disclosure, an ESD protection device is provided that includes a series connection of a first unit having strong snapback and low series capacitance and a second high-voltage unit that displays a relatively high holding/trigger voltage to ensure latch up and improper triggering of the ESD protection device while at the same time providing high-voltage operation with low capacitive loading.

A surge protective device includes an overvoltage protection circuit and a control module coupled to the overvoltage protection circuit that is configured to monitor at least one performance characteristic of the overvoltage protection circuit and is further configured to communicate the at least one performance characteristic to a destination external to the surge protective device.

An over-voltage protection system is provided for use with electrical equipment. The system includes a protection circuit having a first bus for receiving electrical power, a second bus for providing power to the equipment and two parallel surge arresters connected between the first bus and ground. A main and backup bushing are arranged in parallel between the first and second bus. The main bushing is arranged in series with a normally closed contact maintaining the main bushing in service by default. The backup bushing is arranged in series with a normally open contact isolating the backup bushing by default. The protection circuit comprises a controller for testing the insulation of the arresters and bushings. The controller is configured to selectively actuate the contacts to selectively isolate, or incorporate, the arresters and bushings in the circuit to facilitate testing and maintenance while maintaining the protection circuit operational.

An over-voltage protection system is provided for use with electrical equipment. The system includes a protection circuit having a first bus for receiving electrical power, a second bus for providing power to the equipment and two parallel surge arresters connected between the first bus and ground. A main and backup bushing are arranged in parallel between the first and second bus. The main bushing is arranged in series with a normally closed contact maintaining the main bushing in service by default. The backup bushing is arranged in series with a normally open contact isolating the backup bushing by default. The protection circuit comprises a controller for testing the insulation of the arresters and bushings. The controller is configured to selectively actuate the contacts to selectively isolate, or incorporate, the arresters and bushings in the circuit to facilitate testing and maintenance while maintaining the protection circuit operational.

An integrated circuit is provided with a protected circuit wherein a first FinFET operably coupled to a signal node is protected against electrostatic discharge voltage damage by a standard cell electrostatic discharge protection circuit which is connected between first and second voltage supplies and which includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply, where the first and second FinFET diodes are each formed with a FinFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.

Provided is an electrostatic discharge protection circuit, including a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor has a first end coupled to a first power rail. The first transistor has a first end coupled to the first power rail, and a control end of the first transistor is coupled to a second end of the first resistor. The second resistor is coupled between a second end of the first transistor and a second power rail. The second transistor has a first end coupled to the first power rail, a control end of the second transistor is coupled to the second end of the first transistor, and a second end of the second transistor is coupled to the second power rail.

An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode and a second transistor. The diode has an anode electrically connected to a gate of the first group III nitride transistor. The second transistor has a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the diode and a source electrically connected to a source of the first group III nitride transistor.