Patent classifications
H02H9/04
Surge protection apparatus
An apparatus includes a first diode and a second diode connected in series between a first voltage terminal and a second voltage terminal, a switch connected between the first voltage terminal and the second voltage terminal, and a clamping threshold circuit connected between a common node of the first diode and the second diode, and a gate of the switch, wherein the clamping threshold circuit is configured such that in response to a voltage surge applied to the common node of the first diode and the second diode, the switch is turned on once the voltage surge is greater than a predetermined threshold.
Surge protection apparatus having embedded fuse
A surge protection apparatus may include an input terminal; an output terminal, the output terminal electrically coupled to the input terminal; a ground terminal, the ground terminal electrically coupled to the input terminal and output terminal; a positive temperature coefficient (PTC) fuse, the PTC fuse connected in electrical series between the input terminal and output terminal; a crowbar device, the crowbar device electrically connected to the ground terminal and output terminal, wherein the crowbar device is in electrical series with the PTC fuse between the input terminal and ground terminal; and a central frame portion, the central frame portion electrically coupled to the input terminal, output terminal and ground terminal, wherein the crowbar device is disposed on a first side of the central frame portion and the PTC fuse is disposed on a second side of the central frame portion, opposite the first side.
Electrostatic discharge protection devices
An electrostatic discharge protection device includes a first well region, a second well region, a first doped region, and a first heavily doped region. The first well region and the second well region are disposed in a semiconductor substrate. The first doped region is disposed in the first well region and the second well region. The first heavily doped region is disposed in the first doped region in the first well region. The first well region and the first doped region have a first conductivity type, and the second well region and the first heavily doped region have a second conductivity type that is the opposite of the first conductivity type.
Power distribution over ethernet connection
In an embodiment, an apparatus includes a source device including a first current limiter and a second current limiter in parallel with each other and a first transformer and a second transformer; a load device includes a third transformer and a fourth transformer in parallel with each other; and an Ethernet cable is electrically coupled between the source device and the load device, the Ethernet cable including first twisted pair lines and second twisted pair lines. A direct current (DC) voltage is provided to the first current limiter and the second current limiter, the first transformer is electrically coupled to an output of the first current limiter, and the second transformer is electrically coupled to an output of the second current limiter. The DC voltage is transmitted to the third transformer and the fourth transformer in parallel with each other via the first twisted pair lines and the second twisted pair lines. The first twisted pair lines and second twisted pair lines are included in an Ethernet cable electrically coupled between the source device and the load device.
DRIVE CIRCUIT OF POWER DEVICE AND DRIVE SYSTEM
Embodiments of this application disclose a drive circuit of a power device and a drive system, to drive the power device by using a small quantity of components. The drive circuit of the power device includes: a drive signal generation circuit, configured to generate a drive signal; a resistor and a capacitor that are connected in series, coupled to the drive signal generation circuit and the power device, and configured to control turn-on and turn-off of the power device based on the drive signal; and a voltage clamp circuit, coupled to the power device, and configured to control a gate voltage of the power device to be not greater than a gate withstand voltage.
DEVICE FOR PREVENTING OVERVOLTAGE-INDUCED DAMAGE CAUSED BY FAULT PROPAGATION IN SAFETY-RELEVANT SYSTEMS
A device controls a safety-relevant electronic system and has a power supply. The power supply is supplied with a battery voltage at a first input terminal and supplies a first supply voltage at a first output terminal which is lower than the battery voltage. A microcontroller for generating a first control signal, provided at a first control output of the microcontroller for processing by way of a control unit, is supplied with the first supply voltage at a second input terminal. A monitoring unit for generating a second control signal, provided at a second control output of the monitoring unit for processing by the control unit, is supplied with the first supply voltage at a third supply potential input terminal. The third supply potential input terminal, the second control output and the second data port of the monitoring unit are configured to be voltage-proof with respect to the battery voltage.
ELECTROSTATIC PROTECTION CIRCUIT AND DISPLAY PANEL
The present disclosure provides an electrostatic protection circuit and a display panel, wherein the electrostatic protection circuit includes a first voltage reference unit configured to divide a voltage between an array substrate row driving signal line and a common electrode line once; a second voltage reference unit configured to divide the voltage between the array substrate row driving signal line and the common electrode line twice; and a charge releasing unit that adjusts charge distribution between the array substrate row driving signal line and the common electrode line based on reference voltages provided by the first voltage reference unit and the second voltage reference unit.
COAXIAL ISOLATOR
A coaxial isolator includes an integrated circuit board, a first body and a second body. The integrated circuit board includes a first surface, a second surface, a signal processing circuit extending along a central axis, two first capacitors, two second capacitors, and a first iron core. The first capacitors are located on the first surface and are respectively disposed on both sides of the signal processing circuit. The second capacitors are located on the second surface and are respectively arranged corresponding to the positions of the first capacitors. The first iron core surrounds the signal processing circuit. A first tube portion of the first body surrounds the integrated circuit board, and a first end portion of the first body is used for connecting with an external device. A second end portion of the second body is used for connecting with another external device.
COAXIAL ISOLATOR
A coaxial isolator includes an integrated circuit board, a first body and a second body. The integrated circuit board includes a first surface, a second surface, a signal processing circuit extending along a central axis, two first capacitors, two second capacitors, and a first iron core. The first capacitors are located on the first surface and are respectively disposed on both sides of the signal processing circuit. The second capacitors are located on the second surface and are respectively arranged corresponding to the positions of the first capacitors. The first iron core surrounds the signal processing circuit. A first tube portion of the first body surrounds the integrated circuit board, and a first end portion of the first body is used for connecting with an external device. A second end portion of the second body is used for connecting with another external device.
Snapback electrostatic discharge protection for electronic circuits
Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.