In a particular implementation, an apparatus to control clamping devices includes a detection circuitry, a clamping device, inverter circuitry, and first and second control circuitry. In response to a first voltage corresponding to a gate terminal of the clamping device, the first control circuitry is configured to generate a second voltage to set the first voltage below a first voltage threshold. Also, in response to the second voltage, the second control circuitry is configured to generate a third voltage to set a voltage of the detection circuitry below a second voltage threshold.

An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

The present disclosure provides a temperature detection circuit. The temperature detection circuit includes: a first comparator, the first comparator having a first negative input terminal, a first positive input terminal and a first output terminal, the first negative input terminal being connected with an output terminal of a temperature sensor, the first positive input terminal being connected with a first reference voltage terminal; a monostable trigger, an input terminal of the monostable trigger being connected with the first output terminal of the first comparator; a low pass filter, an input terminal of the low pass filter being connected with an output terminal of the monostable trigger. The present disclosure further provides a temperature sensor device and a display device.

Electric power is transferred to an electric load as alternating current over at least two incoming and outgoing lines. At least one line circuit manages at least one parameter of the transferred electric power. A central circuit exchanges data and/or commands with the at least one line circuit over a respective galvanically isolated communication interface, such that a reference potential of the central circuit is floating relative to an earth potential of the at least two incoming and outgoing lines. A respective surge protection capacitor is arranged in parallel with each galvanically isolated communication interface. The surge protection capacitors are configured to accumulate a respective fraction of an electric charge resulting from an undesired overvoltage on one of said incoming lines so as to split up the undesired overvoltage into two or more voltages over the galvanically isolated communication interfaces each of which voltage is smaller than the undesired overvoltage.

Electric power is transferred to an electric load as alternating current over at least two incoming and outgoing lines. At least one line circuit manages at least one parameter of the transferred electric power. A central circuit exchanges data and/or commands with the at least one line circuit over a respective galvanically isolated communication interface, such that a reference potential of the central circuit is floating relative to an earth potential of the at least two incoming and outgoing lines. A respective surge protection capacitor is arranged in parallel with each galvanically isolated communication interface. The surge protection capacitors are configured to accumulate a respective fraction of an electric charge resulting from an undesired overvoltage on one of said incoming lines so as to split up the undesired overvoltage into two or more voltages over the galvanically isolated communication interfaces each of which voltage is smaller than the undesired overvoltage.

A device control method includes: receiving a turn-on signal of a target device, the turn-on signal being adapted to trigger the target device to start working; obtaining a compensation duration, the compensation duration being adapted to offset a delay caused when a voltage zero-crossing detection component detects voltage zero-crossing; and when a zero-crossing signal is received, after the compensation duration, controlling a designated component in the target device to be turned on or off. The zero-crossing signal is a signal sent when the voltage zero-crossing detection component detects that a voltage passes through a zero point. A power supply voltage detection method and a power supply voltage detection apparatus are also disclosed.

A current limiting circuit of a switching circuit, and a switching circuit are provided. The switching circuit uses a gallium nitride (GaN) power transistor as a main power transistor. The current limiting circuit includes a first terminal connected with a drain of the GaN power transistor, and a second terminal connected with a controller of the switching circuit. The current limiting circuit is configured to limit a current flowing out of a power supply terminal of the controller. The current limiting circuit suppresses a negative current flowing through the controller.

A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.

An ESD protection circuit includes a power MOS transistor disposed between a first line and a second line, a clamp circuit disposed between the first line and a first node to which a gate of the power MOS transistor is coupled, a first resistor disposed between the first node and the second line, a MOS transistor disposed between the first node and the second line, a third line supplied with a third potential generated by a constant-voltage circuit of the protection target circuit, and a second resistor and a first capacitor coupled in series between a second node coupled to the third line and the second line, wherein when defining a junction between the second resistor and the first capacitor as a third node, a gate of the MOS transistor is coupled to the third node.